J.S. Kenney

Behavioral modeling of nonlinear RF power amplifiers considering memory effects

This paper proposes a new behavioral model to treat memory effects in nonlinear power amplifiers (PAs). Phenomena such as asymmetries in lower and upper intermodulation terms, and variation of AM/AM and AM/PM, depending on signal history, are often observed in high-power PAs. To treat these phenomena, this paper presents a model based on the previously developed memory polynomial model. The contribution made in this paper is to augment the memory polynomial model to include a sparse delay tap structure that reduces the parameter space required for accurate model identification. A figure-of-merit, called the memory effect ratio, is defined to quantify the relative level of distortion due to memory effects, as compared to the memoryless portion. Another figure-of-merit is defined as the memory effect modeling ratio, which quantifies the degree to which the PA memory effects have been accounted for in the model. This new technique is validated using a variety of RF PAs, including an 880-MHz and a 2.1-GHz high-power laterally diffused metal-oxide semiconductor PA and various signals such as two-tone, eight-tone, and IS-95B signals.

Quantifying memory effects in RF power amplifiers

This paper proposes a system-level behavioral model for RF power amplifiers (PAs), which exhibit memory effects, that is based on the parallel Wiener system. The model extraction is performed using two-tone intermodulation distortion (IMD) measurements with different tone frequency spacings and power levels. It is found that by using such a model, more accurate adjacent-channel power-ratio levels may be predicted for high PAS close to the carrier frequency. This is validated using IS-95B CDMA signals on a low-power (0.5 W) class-AB PA, and on a high-power (45 W) class-B PA. The model also provides a means to quantify memory effects in terms of a figure-of-merit that calculates the relative contribution to the IMD of the memoryless and memory portion of the PA nonlinearity. This figure-of-merit is useful in providing an estimate of the amount of correction that a memoryless predistortion system may have on PAS that exhibit memory effects.

A hybrid digital/RF envelope predistortion linearization system for power amplifiers

This paper presents an adaptive wide-band digitally controlled RF envelope predistortion linearization system for power amplifiers (PAs). A field-programmable gate-array-based lookup table is indexed by a digitized envelope power signal, and instantaneously adjusts the input signal amplitude and phase via an RF vector modulator to compensate for the AM-AM and AM-PM distortion. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20%-33% wider correction bandwidth is achievable at the same clock speeds, and linearization can be performed without the need for a digital baseband input signal. The timing match between the input RF signal and predistorting signal, which is one of the critical factors for performance, was investigated and adjusted to obtain optimum performance. Using three-carrier cdmaOne and wide-band multitone signals, the linearization performances for a 0.5-W GaAs heterostructure field-effect transistor, a 90-W peak-envelope-power (PEP) silicon LDMOS PA, and a 680-W PEP LDMOS PA were examined. In addition, the predistortion performance variation for different signals was studied in terms of signal envelope statistics, output powers, and PA power capacities.

A wide-band reflection-type phase shifter at S-band using BST coated substrate

The design and experimental results of a wide-band monolithic reflection-type phase shifter are presented in this paper. The phase shifter fabricated on Ba/sub 0.6/Sr/sub 0.4/TiO/sub 3/ (BST)/sapphire consists of a coplanar waveguide (CPW) Lange coupler, a series resonated LC termination, and a bias network. The CPW Lange coupler results in a power split of 3.5 dB/spl plusmn/0.5 dB in the range of 1.6-3.2 GHz. The BST interdigital capacitor has a tunability (C/sub max//C/sub min/) of 3.1 with 140 V. Measured and simulated performance of a series resonated LC termination was described. The phase shifter has achieved a phase-shift range of over 90/spl deg/ with an insertion loss of better than 2.0 dB and a return loss of higher than 14 dB in the frequency range of 1.9-2.5 GHz over a bias voltage range from 0 to 160 V. A figure-of-merit of maximum 72/spl deg//dB at 2 GHz was obtained. The smaller phase shifter using the folded-type CPW Lange coupler, which maintains a smaller aspect ratio for easier packaging, has an insertion loss of better than 2.3 dB with a phase-shift range of over 130/spl deg/ at 2.5 GHz. Two-tone measurements of the phase shifter indicate an input IP/sub 3/ of 32 dBm with 0 V and 41.9 dBm with 60 V. Total size of the monolithic BST phase shifter is 11.2 mm /spl times/ 4.9 mm /spl times/ 0.43 mm for the straight coupler design and 5.4 mm /spl times/ 6.5 mm /spl times/ 0.43 mm for the folded-type design.

A reduced intermodulation distortion tunable ferroelectric capacitor-architecture and demonstration

A ferroelectric tunable capacitor device architecture is presented that allows for a reduction of intermodulation distortion (IMD), while maintaining high tunability at low bias voltages. The tunable capacitor is fabricated from epitaxial thin-film barium-strontium-titanate deposited on a sapphire substrate. The RF portion of the capacitor is a conventional planar gap capacitor with a 12-14-/spl mu/m gap. However, rather than superimposing the dc bias on the RF pads, a separate bias structure is fabricated within the RF gap. The interdigital bias structure has narrowly spaced high resistance (2-3/spl times/10/sup 4/ /spl Omega//sq) oxide conductor electrodes, such as indium-tin-oxide electrodes or lanthanum-strontium-cobalt-oxide electrodes spaced 1-2 /spl mu/m apart. The high resistivity of the bias electrodes decouples the dc bias from the RF signal path. This bias structure allows high dc fields to be developed with less than 30 V applied to tune the material permittivity (1 : 1.4), but is sufficiently resistive to avoid affecting the Q factor of the RF capacitor. Since the RF gap is wide, the IMD performance remains good, even at modest tuning voltages. The following three classes of gap capacitor have been fabricated for concept verification: 1) a conventional gap structure (without additional bias structure); 2) the proposed RF gap capacitor with the dc-bias structure; and 3) a narrower conventional RF gap-capacitor structure used as an IMD reference. The proposed RF gap capacitor with dc-bias structure has been fabricated in two versions: one in which the highly resistive bias electrodes are electrically connected to the RF electrodes (the attached-bias-electrode (ABE) scheme) and one in which the highly resistive electrodes are provided with a separate port for further control (the isolated-bias-electrode (IBE) scheme). In addition, parallel and perpendicular orientation of the bias electrodes relative to the RF field is investigated. The frequency response of the proposed gap capacitor with the dc-bias structure is characterized and its analysis shows that the highly resistive bias lines are serving as a dc-bias path for high tunability, but are not attenuating the RF signal. While the IBE structure has more degrees of freedom for biasing as compared to the ABE structure, the overall tunability at 30 V and IMD performance of both the ABE and IBE structures are similar. Two-tone IMD tests show that the IMD performance for the gap capacitor with the bias structure is improved by 6 dB over the conventional reference structure at the same tunability.

A low voltage W-CDMA polar transmitter with digital envelope path gain compensation

This letter presents a polar transmitter using a dual-phase pulsewidth-modulated buck converter with a 50-MHz effective switching frequency. Using a wideband code division multiple access voice signal, the overall system can achieve 52.8% drain efficiency (49.8% power added efficiency) at 24-dBm output power at 836.5MHz with a 3.5-V supply voltage, while passing both adjacent channel leakage power ratio (ACLR1) and alternate channel leakage power (ACLR2) specifications. A digital finite impulse response filter is included in the envelope path to compensate for gain roll-off at higher baseband frequencies. This envelope path compensation allows greater linear bandwidth to be achieved at lower switching frequencies, thus boosting efficiency, and improving ACLR by as much as 8dB. The polar transmitter is characterized over a supply voltage of 2.5-4.5V, making it well suited for battery powered, handheld applications

Extraction of accurate behavioral models for power amplifiers with memory effects using two-tone measurements

This paper proposes a system-level behavioral model for RF power amplifiers (PAs) that exhibit memory effects. PAs with memory effects are shown to have two-tone intermodulation distortion (IMD) levels that vary depending on tone-spacing. Thus, typical single tone extracted AM/AM and AM/PM characteristics cannot accurately model PA memory effects. By varying the frequency spacing of two-tone signals, envelope frequency dependent transfer functions can be derived. Using these transfer functions, a behavioral model is developed which is based on the parallel-cascade linear and nonlinear (LN) system. This model gives more accurate results in predicting the behavior of PAs with memory effects close to the carrier frequency. The model is validated by comparing the predicted and measured adjacent channel power ratio (ACPR) of a CDMA signal amplified by a high power class-AB PA. It is found that the parallel cascade model improves ACPR prediction accuracy by as much as 4 dB compared to the single tone derived memoryless model.

Identification of RF Power Amplifier Memory Effect Origins using Third-Order Intermodulation Distortion Amplitude and Phase Asymmetry

This paper describes a technique to determine the physical origins of memory effects in RF power amplifiers using amplitude and phase asymmetries of two-tone third order intermodulation distortion (IMD) products measured over a range of power levels and frequency spacing. Determining the origins of the memory effects is done by extracting the portion of the IMD product in each sideband that contributes to the asymmetry, and comparing these on a statistical basis to the responses of simple equivalent circuit models that represent thermal self-heating, and bias voltage feedback. A 90W, singled-ended GaN pHEMT PA stage is compared to a 650W push-pull combined Si LDMOS PA at 2.14 GHz. It is shown that the GaN PA memory effects are dominated by bias feedback (which is later improved), and that the LDMOS PA memory effects are dominated by thermal self-heating. These results are further quantified by comparing memory ratios

Power amplifier linearization with digital pre-distortion and crest factor reduction

This paper investigates the use of crest factor reduction (CFR) as a cost-effective method of increasing output power and efficiency for power amplifiers (PAs) operating in conjunction with pre-distortion linearization system. Previous result indicated adjacent and alternate channel leakage ratio (ACLR) improvements of 10-12 dB were obtained from memoryless pre-distortion of a high power amplifier using a standard IS-95 signal with a peak-to-average ratio of approximately 9.6 dB. This paper investigates the effect of using CFR data in conjunction with the same digital pre-distortion platform. It was found that using CFR with pre-distortion allows for an increase of 2.7 dB in output power while maintaining the same ACLR of -45 dBc at 885 KHz offset on a 30W LDMOS PA. Furthermore, due to the decreased output back-off an effective efficiency improvement of 5.6% was also realized.

A Dual-Mode CMOS RF Power Amplifier With Integrated Tunable Matching Network

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-μm CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far.