Wangmyong Woo

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.

A hybrid digital/RF envelope predistortion linearization system for power amplifiers

This paper presents an adaptive wide-band digitally controlled RF envelope predistortion linearization system for power amplifiers (PAs). A field-programmable gate-array-based lookup table is indexed by a digitized envelope power signal, and instantaneously adjusts the input signal amplitude and phase via an RF vector modulator to compensate for the AM-AM and AM-PM distortion. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20%-33% wider correction bandwidth is achievable at the same clock speeds, and linearization can be performed without the need for a digital baseband input signal. The timing match between the input RF signal and predistorting signal, which is one of the critical factors for performance, was investigated and adjusted to obtain optimum performance. Using three-carrier cdmaOne and wide-band multitone signals, the linearization performances for a 0.5-W GaAs heterostructure field-effect transistor, a 90-W peak-envelope-power (PEP) silicon LDMOS PA, and a 680-W PEP LDMOS PA were examined. In addition, the predistortion performance variation for different signals was studied in terms of signal envelope statistics, output powers, and PA power capacities.

A new envelope predistortion linearization architecture for handset power amplifiers

The paper proposes a new envelope predistortion linearization architecture that utilizes low power analog components to correct intermodulation distortion (IMD) in RF power amplifiers (PAs). Log amps and phase detectors are used at the input and output of the PA to estimate the instantaneous complex gain. The outputs of the log amps and phase detector are fed back to a voltage controlled variable attenuator (VVA) and phase shifter (VVP), respectively, to correct any errors in the gain due to AM-AM or AM-PM distortion. As opposed to traditional envelope feedback approaches, this architecture achieves greater bandwidth by only feeding the distortion components back. Moreover, the distortion components are not added to the input signal as feedback, but they are used to predistort the input signal in a multiplicative manner. This architecture also allows correction of envelope memory effects that may occur in the PA. A behavioral model for Class-AB PA has been developed. The architecture has been verified by means of computer simulation using behavioral models extracted from a VVA, a VVP, and a 0.5 W GaAs HFET PA. For a cdmaOne signal with a bandwidth of 1.2288 MHz, the simulation shows an ACPR peak improvement of more than 10 dB over an output power dynamic range of 6 dB.

A predistortion linearization system for high power amplifiers with low frequency envelope memory effects

This paper proposes an RF envelope predistortion linearization system that utilizes a combination of an analog envelope predistortion (APD) working in conjunction with a digital look-up table (LUT) based adaptive envelope predistortion (DPD). The APD system is used as an inner loop to correct slowly varying changes in gain, effectively compensating for long time constant memory effects. The DPD forms the outer loop that corrects the distortion over a wide bandwidth. The APD/DPD combination showed up to 6 dB improvement over the DPD alone for a 90W PEP power amplifier.

Adaptive predistortion linearization of RF power amplifiers using lookup tables generated from subsampled data

This paper discusses a new architecture for adaptive predistortion linearization of power amplifiers, whereby subsampled data (i.e. lower than Nyquist rate) from the input and output baseband waveforms is used to construct a lookup table. The technique utilizes a sampling downconverter that accurately captures a waveform sample in a narrow aperture before digitization. Because aliasing effects are the same for both input and output waveforms, information may be obtained regarding the amplitude and phase distortion characteristics of the power amplifier. The concept is validated using a test bed consisting of two sampling downconverters and a dual channel receiver. Results achieved indicate that 10-12 dB of adjacent channel power ratio (ACPR) improvement may be obtain using sampling rates as low as 33% of the Nyquist rate of the baseband output signal bandwidth.

Predistortion linearization system for high power amplifiers

This paper presents an adaptive wideband, digitally controlled RF envelope predistortion linearization system for high power amplifiers. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20/spl sim/33% wider correction bandwidth is achievable at the same clock speeds, and it can perform linearization without the need for a digital baseband input signal. Using 3-carrier CDMAOne and wideband multi-tone signals, the linearization performances for a 90W PEP LDMOS PA and a 680W PEP LDMOS PA were examined.

A high power CMOS SP4T switch using a switched resonator for dual band applications

A novel dual-band CMOS SP4T switch with P1dB of higher than 31 dBm is designed to operate at 0.9 GHz and 1.8 GHz. In the Rx switch path, a carefully designed switched resonator is incorporated in order to block high RF signal power from the power amplifier at the Tx path as well as to maintain low insertion loss in the Rx mode simultaneously. In Tx switch devices, a body substrate tuning technique is applied to maintain high power delivery to antenna port. Extended simulation results demonstrate more than 31 dBm of P1dB at both low and high bands as well as 0.9 dB and 1.4 dB of insertion loss at 900 MHz and 1.9 GHz, respectively. To the best of our knowledge, the proposed RF switch shows the highest P1dB with a bulk CMOS based RF switch ever published. This paper also demonstrates the feasibilities of CMOS integration of RF front-end switch modules for modern wireless communication applications.

Wideband predistortion linearization system for RF power amplifiers using an envelope modulation technique

This paper proposes a wideband adaptive predistortion linearization system based on high-speed RF envelope modulation applied to the input signal of an RF power amplifier. An FPGA-based look-up table, fed by a digitized envelope power signal, controls the envelope modulation performed by an RF vector modulator. The advantages of this predistortion architecture over conventional baseband digital approaches are a wider bandwidth, and the elimination of the need for digital baseband I/Q streams. The predistortion system was implemented as a testbed. Using 3-carrier CDMA2000 and multi-tone signals, the linearization performances for a 0.5 W GaAs HFET and a 90 W peak envelope power (PEP) LDMOS power amplifier were examined on the testbed. In the third-order intermodulation distortion (IMD) region, the wideband multi-tone testing showed IMD suppressions of 9 to 13 dB over 63 MHz bandwidth and a range of 7 to 8 dB backoff. For the 90 W power amplifier, the system achieved adjacent channel power ratio (ACPR) improvement of 13 dB output power backoff.

Mixed-signal behavioral simulation of an envelope predistortion linearization system for RF power amplifiers

This paper presents a mixed-signal behavioral simulation for an RF power amplifier predistortion system. The predistortion architecture is based on FPGA-based look-up tables that drive RF vector modulators. Behavioral models are extracted from the RF components and simulated in the same file with the digital components. Trade-offs are made between the FPGA design and the RF component design to optimize the performance of the system.

A novel linear polar transmitter architecture using low-power analog predistortion for EDGE applications

This paper presents a new polar transmitter architecture that employs analog predistortion to provide substantially instantaneous correction of amplitude and phase errors in RF PAs. This approach enables to enhance the linear output power capability and efficiency of a PA, simultaneously. Unlike conventional architectures using a closed-loop feedback, no downconversion receiver is included in the transmitter. Moreover, only even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. For validation of the architecture, a PA circuit model was designed, based upon the TSMC 0.18-um CMOS technology. In the simulation results, the proposed architecture reduced PA nonlinearity from 2 dB to 0.5 dB for gain and from 18deg to plusmn0.5deg for phase. Also, the simulation results exhibited EVMs of less than 0.5% in RMS and 5% in peak, a PAE of 58% at the output power of 33 dBm.