J. Sone

Transistor characteristics of 14-nm-gate-length EJ-MOSFETs

We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFETs) to investigate transport characteristics of ultrafine gate MOSFETs. By using EB direct writing on an ultrahigh-resolution negative resist (calixarene), we could achieved a gate length of only 14 nm. Despite such an ultrafine gate, the device exhibited transistor operation at room temperature. From studying the devices with the gate lengths from 14 nm to 98 nm, we found that when the gate length was below 30 nm the subthreshold leakage current increased. The low-temperature measurements showed that the leakage current was caused by the classical thermal process and that quantum effects do not play an important role in subthreshold characteristics at room temperature.

Transistor operation of 30-nm gate-length EJ-MOSFETs

We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFETs) to investigate transistor characteristics of ultrafine-gate MOSFETs. By using EB direct writing onto an ultrahigh-resolution negative resist (calixarene), we achieved a gate length of 32 nm for the first time. The short-channel effects were effectively suppressed by electrically induced ultrashallow source/drain regions, and the fabricated device exhibited normal transistor characteristics even in the 32-nm gate-length regime at room temperature: an ON/OFF current ratio of 10/sup 5/ and a cut-off current of 20 pA//spl mu/m.

Proposal of Pseudo Source and Drain MOSFETs for Evaluating 10-nm Gate MOSFETs

We propose a Pseudo source and drain metal oxide semiconductor field effect transistors (Ps-MOSFET) for investigating the electrical characteristics and physical phenomena in 10-nm gate MOSFETs. The Ps-MOSFET consists of a lower gate and an upper gate which electrically induce pseudo source and drain regions at the silicon surface. In this structure, the pseudo source/drain regions act as doped source/drain regions in a MOSFET. Since the pseudo source/drain regions are extremely shallow, short-channel effects are expected to be suppressed in this structure. To minimize the channel length and the leakage current, we optimized the substrate doping concentration to be approximately 1018 cm-3 by using a two-dimensional numerical simulation. In this case, we obtained a channel length of approximately 16 nm for 10-nm gate Ps-MOSFETs. Under this optimal doping condition, numerical calculations showed satisfactory transistor operations for the 10-nm gate Ps-MOSFETs: ON/OFF current ratio ?106 and subthreshold slope ?100 mV/decade. We also showed by calculation that the direct source-drain tunneling current was not negligible in the sub-10-nm regime.

Current-voltage characteristics of p -Ge/n-GaAs heterojunction diodes grown by molecular beam epitaxy

Electrical characteristics ofp-Ge/n-GaAs heterojunctions on GaAs(l00) grown by molecular beam epitaxy (MBE) have been investigated. Thep-type Ge layer was produced by intentionally doping with Ga atoms, in addition to the diffusion of Ga atoms from the surface of the GaAs layer. The best ideality factor of 1.04 over six decades of the forward current and the lowest reverse current density of the order of 10−6 A/cm2 were obtained for diodes with Ge grown at 500° C. The ideality factor increased slightly up to 1.12 when the operating temperature was decreased to 77 K. By studying the temperature dependence of the forward current, the conduction band discontinuity has been estimated to be 40 ± 10 meV. The suppression of Ga diffusion into the Ge film and its effect on pn-junction characteristics were also studied by growing a thin Ge film on GaAs at less than 300° C prior to the normal Ge film growth at 500° C.

Numerical Studies on Quantum Transport in Antidot Arrays in Magnetic Fields

The density of states and the conductivity tensor in antidot arrays in magnetic fields are calculated numerically by the self-consistent Born approximation (SCBA). The peak positions of the density of states agree well with the quantization condition for several short-periodic orbits. The behavior of calculated magnetoresistivity agrees with that of experimental data. However, the behavior of the conductivity tensor is very complicated, and it is not explained simply by the periodic orbit expression for the conductivity tensor.

Current-injection Josephson latch employing a single-flux quantum. I

A novel current‐injection Josephson latch with a single‐flux quantum memory is experimentally verified. The experimental latch is fabricated by 5‐μm Pb‐alloy technology and occupies an area of 270×175 μm2, achieving one order of magnitude area reduction compared to magnetically coupled latch. In low‐frequency experiments, the proper operation of a single latch under arbitrary input conditions and the proper data transfer from latch to latch are observed. In high‐speed experiments, the proper operation of a single latch with cycle time down to 3.7 ns is observed, which is limited by the high‐speed restriction of the test instruments at room temperature. These results show the possibility that the complete current injection logic system can be constructed by combining the present latch and current‐injection logic gates.

Turn‐on delay analysis of current‐injection Josephson logic circuits

A turn‐on delay, during which the output voltage of a Josephson logic circuit is very small, is of prime interest for the design of high‐speed Josephson digital integrated circuits. We have derived an analytical formula for the turn‐on delay of the current‐injection logic circuits, which is in good agreement with computer simulations. Analysis of the circuit equations shows that the nonlinear inductance of a current‐summing Josephson junction plays an important role for the turn‐on delay. Dependences of the turn‐on delay on circuit parameters and operating conditions are calculated. For parameter values typical of 5‐μm current‐injection circuits, the turn‐on delay is on the order of 10 ps. The turn‐on delay and operating margin are compared in various types of current‐injection logic circuits. The higher sensitivity of the threshold gate current to the input current is found to be desirable not only to reduce the turn‐on delay but to operate in a wide margin.

Tunneling of quasiparticles in the normal-insulator-superconductor-insulator-normal geometry

The probability of quasiparticle transmission going through a normal‐insulator‐ superconductor‐insulator‐normal (NISIN) geometry is theoretically calculated using Bogoliubov–de Gennes equations to investigate the feasibility of electron devices utilizing this geometry. This new calculation is able to include a current carried by Cooper pairs by employing hole injections from the outlet which destroy Cooper pairs at the outlet super‐ conductor‐insulator boundary. Resonant tunneling phenomena occur even if the electron kinetic energy is less than the superconducting energy gap and electron tunneling probabilities are greatly modified by the resonance. When the unevenness of the superconductor (S) width thickness is large compared with the electron wavelength in the S layer, the resonance is smeared out in averaged tunneling probabilities. Then the tunneling probabilities can be controlled by the electron kinetic energy. Applications of the NISIN geometry for superconducting transistors are also discussed.

Properties of a Poly-Si/GaAs layered structure on Si for Si heterojunction bipolar transistor

The properties of poly-Si/GaAs layered films on Si for use in wide bandgap emitters for Si heterojunction bipolar transistors (Si-HBTs), were studied. A smooth GaAs film surface grown on Si was obtained at low temperature (200° C) from the initial stage of growth. The x-ray diffraction (XRD) results indicated that strong GaAs orientation (111) was obtained for the poly-Si/GaAs/Si-substrate layered structure after annealing at 800° C for 20 sec. Secondary ion mass spectroscopy (SIMS) profiles indicated that impurity diffusion from the GaAs layer into the p-type Si substrate was negligible at 800° C. The electrical characteristics forn-poly-Si/n-GaAs/p-Si-substrate heterojunction diodes were also investigated.

Poly-Si/GaAs Layered Structure on Si as a Wide Bandgap Emitter for Si Heterojunction Bipolar Transistor

The properties of poly-Si/GaAs layered filns on Si for use in a wide bandgap emitter for Sl heteroJunction blpolar transistors (Si-HBTs), were studied. A smooth GaAs filn surface, grown on Si, was obtained at low tenperature (200oC) fron the initial stage of growth. The X-Ray Diffraction (XRD) results lndlcated that strong GaAs orientation (fff) was obtalned for the poly-Si/GaAs/Si-substrate layered structure after anneallng at 800oC for 20 seconds. Secondary Ion Mass Spectroscopy (SIMS) proflles lndlcatetl that lnpurlty dlffuslon fron GaAs layer into the p-type Si substrate was negllglble at 800oC.