Jabulani Nyathi

On nanoelectronic architectural challenges and solutions

This paper discusses the many challenges in the design of future nano architectures that result from the use of nanoelectronic devices. The relations among these challenges are studied, and an unfortunately subjective relative ranking is proposed. Possible solutions are suggested.

A VLSI high-performance encoder with priority lookahead

In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worst case operation of the circuit, while maintaining a very low transistor count. The encoders topmost input request has the highest priority; this priority descends linearly. Two design approaches for the priority encoder are presented, one without a priority lookahead scheme and one with a priority lookahead scheme. For an N-bit encoder, the circuit with the priority lookahead scheme requires only 1.094 times the number of transistors of the circuit without the priority lookahead scheme. Having a 32-bit encoder as an example, the circuit with the priority lookahead scheme is 2.59 times faster than the circuit without the priority lookahead. The worst case operation delay is 4.4 ns for this lookahead encoder, using a 1-/spl mu/m scalable CMOS technology. The proposed lookahead scheme can be extended to larger encoders.

Logic circuits operating in subthreshold voltages

In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6times better than the static CMOS configuration while dissipating 18% less power

Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations

Interest in subthreshold design has increased due to the emergence of systems that require ultra-low power and the ever increasing leakage currents (now used to drive logic). Subthreshold sacrifices speed for power creating a clear divide between designing for high speed and ultra-low power. It might be beneficial to allow subthreshold circuits to operate in super-threshold, depending on processing needs. In this paper, the feasibility of optimizing device sizes for both subthreshold and above threshold operations is considered. In addition body biasing techniques that could facilitate bridging the speed gap are presented Device sizing for circuits of the subthreshold region is examined with the view that these circuits could be optimized for subthreshold but also operate effectively in super-threshold. In an effort to attain optimal performance (speed-power), an operating region is identified in terms of the energy-delay product. To enhance the operating speed of both subthreshold and super-threshold circuits, a novel body biasing technique termed tunable body biasing (TBB), is introduced This approach leads to increased operating frequencies particularly in subthreshold operation and shows no performance degradation at voltages above threshold, hence bridging of the speed gap. Post layout simulations of circuits ranging from simple to more complex ones enable for effective evaluation of optimal device sizing and identifying the optimal power-speed operational region. Simulations have been performed at a modest 180 nm technology node and circuits show optimal operating regions ranging from 0.5 to 1.1 V. Further more results indicate that the TBB approach for an inverter triples speed and has a 60 percent lower EDP while dissipating just 28 percent more energy than a traditionally biased approach (pMOS bulk at VDD and nMOS bulk at Vss).

On the advantages of serial architectures for low-power reliable computations

This paper explores low power reliable micro-architectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V/sub th/). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180nm, 120 nm, and 70nm) identify the supply voltages where the power-delay and energy-delay products are minimized. These show that redundant serial adders are not only low power and reliable, but can trade speed for power in a wide range (by varying V/sub DD/ both above and below V/sub th/).

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Clock skew and clock distribution are increasingly becoming a major design concern in synchronous pipelined systems. We present a novel high-speed hybrid wave-pipelined linear feedback shift register that manages clock skew by permitting the clock to travel with its associated data through the pipeline. The wave-pipelined clock has a skew 8.34 times lower than that of a buffered clock and is 1.2 times faster.

A VLSI interconnection network router using a D-CAM with hidden refresh

A VLSI implementation of a programmable router scheme for parallel interconnection network architectures is presented in this paper. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. To further increase throughput, the router operation has been made pipelined, achieving 1 routing decision per cycle. The implementation is based on a content addressable memory (CAM) that supports per entry unique bit masking. This programmable CAM requires few entries; this in turn makes it possible to implement a dynamic approach in order to reduce the transistor count. We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the CAM, we have incorporated a fast priority scheme that allows only one entry to be selected and a memory that stores the port assignment. The number of required CAM entries is extremely small; it is of the same order as the output ports.

Performance of CNFET SRAM cells under diameter variation corners

In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, and performance under diameter variation corners. The carbon nanotube FET is currently considered to be the possible “beyond CMOS” device due to its1-D transport properties that include low carrier scattering and ballistic transport. The memory cells are classified by their transistor count (6-, 7- and 8-transistor cell.) Under a nominal diameter of 1.51nm, the 8-T cell has the lowest delay and energy consumption of 3.7ps and 0.348fJ, respectively. Simulations with transistor diameter variations show that small n-type device diameters result in significantly slow read and write delays. The 8-transistor cell dissipates the least energy when the transistor diameters range from 1.369nm to 1.659nm.

Self-timed refreshing approach for dynamic memories

Refreshing dynamic circuits must be carried out before stored voltages reach unacceptable levels. In this paper we present CMOS circuitry that can be used to sense the integrity of stored data, provide timely refreshing to these dynamic circuits and provide high performance. Differential amplifiers are used to provide the difference between a degrading stored voltage and a reference voltage. This difference gets converted to a single-ended output which serves as the refresh trigger. Memory arrays are used as test beds to verify the functionality and effectiveness of these circuits. The circuits considered in this paper are suitable for use in high speed, low power and high density memory arrays.

Multiple clock domain synchronization for network on chip architectures

The Network-on-Chip (NoC) is emerging as a revolutionary methodology in solving the performance limitations arising out of long interconnects. Continued advancement of NoC designs is heavily dependent on the ability to effectively communicate among the constituent Intellectual Property (IP) blocks/Embedded cores, as well as manage/reduce energy dissipation. This paper presents a low-latency, low-energy synchronization mechanism for Network on Chip architectures, which enables the network to span a system-on-chip (SoC) with multiple independent clock domains. The proposed interface scheme has been compared to another existing scheme and shown to outperform it in terms of latency and energy dissipation.