José G. Delgado-Frias

VLSI for Artificial Intelligence

1 Prolog Machines.- 1.1 From Low Level Semantic Description of Prolog to Instruction Set and VLSI Design.- 1.2 A 32 Bit Processor for Compiled Prolog.- 1.3 CARMEL-1: A VLSI Architecture for Flat Concurrent Prolog.- 1.4 VLSI for Parallel Execution of Prolog.- 2 Functional Programming Oriented Architectures.- 2.1 Supporting Functional and Logic Programming Languages through a Data Parallel VLSI Architecture.- 2.2 Translating Declaratively Specified Knowledge and Usage Requirements into a Reconfigurable Machine.- 3 Garbage Collection.- 3.1 VLSI-Appropriate Garbage Collection Support.- 3.2 A Self-timed Circuit for a Prolog Machine.- 4 Content-Addressable Memory.- 4.1 VLSI and Rule-Based Systems.- 4.2 Unify with Active Memory.- 4.3 The Pattern Addressable Memory: Hardware for Associative Processing.- 5 Knowledge Based Systems.- 5.1 A High Performance Relational Algebraic Processor for Large Knowledge Bases.- 5.2 A WSI Semantic Network Architecture.- 6 Neural Architectures.- 6.1 A VLSI Implementation of Multilayered Neural Networks.- 6.2 A Fully Digital Integrated CMOS Hopfield Network Including the Learning Algorithm.- 6.3 A Neural Network for 3-D VLSI Accelerator.- 6.4 Shift Invariant Associative Memory.- 7 Digital and Analog VLSI Neural Networks.- 7.1 VLSI Bit-Serial Neural Networks.- 7.2 A New CMOS Architecture for Neural Networks.- 7.3 A Limited-Interconnect, Highly Layered Synthetic Neural Architecture.- 7.4 VLSI-Design of Associative Networks.- 7.5 Fully-Programmable Analogue VLSI Devices for the Implementation of Neural Networks.- 8 Architectures for Neural Computing.- 8.1 Are Special Chips Necessary for Neural Computing?.- 8.2 A VLSI Systolic Array Dedicated to Hopfield Neural Network.- 8.3 An Integrated System for Neural Network Simulations.

Sigmoid generators for neural computing using piecewise approximations

A piecewise second order approximation scheme is proposed for computing the sigmoid function. The scheme provides high performance with low implementation cost; thus, it is suitable for hardwired cost effective neural emulators. It is shown that an implementation of the sigmoid generator outperforms, in both precision and speed, existing schemes using a bit serial pipelined implementation. The proposed generator requires one multiplication, no look-up table and no addition. It has been estimated that the sigmoid output is generated with a maximum computation delay of 21 bit serial machine cycles representing a speedup of 1.57 to 2.23 over other proposals.

Elementary function generators for neural-network emulators

Piece-wise first- and second-order approximations are employed to design commonly used elementary function generators for neural-network emulators. Three novel schemes are proposed for the first-order approximations. The first scheme requires one multiplication, one addition, and a 28-byte lookup table. The second scheme requires one addition, a 14-byte lookup table, and no multiplication. The third scheme needs a 14-byte lookup table, no multiplication, and no addition. A second-order approximation approach provides better function precision; it requires more hardware and involves the computation of one multiplication and two additions and access to a 28-byte lookup table. We consider bit serial implementations of the schemes to reduce the hardware cost. The maximum delay for the four schemes ranges from 24- to 32-bit serial machine cycles; the second-order approximation approach has the largest delay. The proposed approach can be applied to compute other elementary function with proper considerations.

FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm

Today most research involving the execution of the Advanced Encryption Standard (AES) algorithm falls into three areas: ultra-high-speed encryption, very low power consumption, and algorithmic integrity. This studys focus is on how to lower the power consumption of an FPGA-based encryption scheme with minimum effect on performance. Three novel FPGA schemes are introduced and evaluated. These schemes are compared in terms of architectural and performance differences, as well as the power consumption rates. The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput.

MARS: Misbehavior Detection in Ad Hoc Networks

To detect misbehavior on data and mitigate adverse effects, we propose and evaluate a MultipAth routing single path transmission (MARS) scheme. The MARS combines multipath routing, single path data transmission, and end-to-end feedback mechanism together to provide more comprehensive protection against misbehavior from individual or cooperating misbehaving nodes. The MARS scheme and its enhancement E- MARS are evaluated by means of simulation under various adverse scenarios. The simulation results show that the MARS and E-MARS schemes provide better network performance and considerable protection to data transmission than some DSR-based transmission systems at the expense of moderate overhead. Compared to the DSR-based schemes, the proposed schemes deliver up to 45% more data with 20% misbehaving nodes under individual misbehavior, and up to 28% more data with 40% misbehaving nodes under colluded misbehavior.

SPIN: a sequential pipelined neurocomputer

A novel digital network architecture, the sequential pipelined neurocomputer (SPIN), is proposed. The SPIN processor emulates neural networks, producing high performance with minimal hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported.<<ETX>>

VLSI for artificial intelligence and neural networks

A selection of 39 papers present novel and emerging approaches to VLSI implementation of machines for artificial intelligence and neural networks. The sections cover architecture and hardware support for artificial intelligence processing, machines for Prolog, analogue and pulse stream neural networ

A flexible bit-pattern associative router for interconnection networks

A programmable associative approach to execute implicit routing algorithms is presented. Algorithms are mapped onto a set of bit-patterns that are matched in parallel. We have studied and mapped a large number of routing algorithms for a wide range of interconnection network topologies. Here we report three cases that illustrate the capabilities of the router scheme. For the studied topologies, the number of required bit-patterns is of the same order as the topology degree. The proposed approach is one of the fastest routers and requires a very small amount of hardware.

HYBRID NEWTON-RAPHSON GENETIC ALGORITHM FOR THE TRAVELING SALESMAN PROBLEM

This paper presents a novel genetic algorithm to solve the traveling salesman problem. The proposed method combines the Newton-Raphson numerical method with an inversion genetic algorithm; the method is called inversion with embedded Newton-Raphson Search. Different benchmark problems, including 10-, 30-, 50-, 75-, 105-, and 318-city topologies, are used to evaluate the approach. The best-known solutions have been produced by this hybrid genetic algorithm. In this paper we also report other results, such as the average tour distance, distribution of the results, and average number of generations. The proposed approach has been shown to outperform other genetic operators. An analysis based on the survival rate of the o-schemata and Hollands fundamental theory is included.

Low power SRAM cell design for FinFET and CNTFET technologies

Implementations of SRAM cells in FinFET and carbon nanotube FET (CNTFET) technologies are presented in this paper. The International Technology Roadmap for Semiconductors has identified these technologies as likely candidates to replace bulk CMOS. Leakage current is one of the major contributors in the power consumption in SRAM arrays; FinFETs have been shown to greatly reduce leakage current. The FinFET memory cells are presented. These cells dissipate 0.49 µW of static power. The CNTFET memory requires 0.195 µW of static power. In current synthesis processes Metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. This CNTFET memory with metallic tolerance dissipates 0.21 µW of static power.