Jacek Bieganowski

Reduction in the number of LUT elements for control units with code sharing

Reduction in the number of LUT elements for control units with code sharing Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

Design of FPGA-based Moore FMSs with counters

Abstract A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The main di_erence form already known methods is that the counter increases its state during conditional and unconditional transitions. An example of application of proposed methods is given.

Microprogram control unit with code sharing and extended microinstruction format

The paper presents a synthesis method that allows reduction of the number of look-up table (LUT) elements in logic circuits of compositional microprogram control units (CMCU) with code sharing. The method is mainly targeted for field-programmable gate arrays (FPGA) with embedded-memory blocks (EMB) but can be also used in case of Complex Programmable Logic Devices (CPLD). The main idea of the method is to use classes of pseudoequivalent operational linear chains, stored in control memory of the unit, to save LUT elements. The article contains conditions for application of the method, example of design and results of synthesis in Xilinx ISE.

Finite State Machines and Field-Programmable Gate Arrays

The Chapter provides some basic information. Firstly, the language of GSA is introduced. Next, the connections are shown with GSAs and state transition graphs of both Mealy and Moore FSMs. Classical principles of FSM logic synthesis are discussed. The basic features of FPGA are analyzed. It is shown that embedded memory blocks allow implementing systems of regular Boolean functions. The modern design flow is analyzed targeting FPGA-based projects. Next, the basic problems of FSM design are considered. Different state assignment methods are analyzed, as well as the methods of functional decomposition. Next the issues are discussed connected with implementing FSM logic circuits with EMBs. The peculiarities of hybrid FPGAs are discussed last part of the Chapter.

Linear Chains in FSMs

The Chapter is devoted to the using linear chains in FSMs. The counter-based microprogram control units are discussed, as well as known PLA-based structures of Moore FSMs. Then there are discussed methods of optimal state assignment and transformation of state codes into codes of classes of pseudoequivalent states (PES). Next there are introduced different linear chains of states (LCS) such as unitary, elementary, normal and extended LCSs. The structural diagrams are proposed for LCS-based Moore FSMs. The proposed procedures are discussed for constructing different linear chains of states.

Hardware Reduction for Moore EFSMs

The Chapter is devoted to hardware reduction targeting the normal LCS-based Moore FSMs. Firstly, the optimization methods are proposed for the base model of NFSM. They are based on the executing either optimal state assignment or transformation of state codes. Two different models are proposed for the case of code transformation. They depend on the numbers of microoperations of FSM and outputs of EMB in use. The models are discussed based on the principle of code sharing. In this case, the state code is represented as a concatenation of the code of normal LCS and the code of component inside this chain. The last part of the chapter is devoted to design methods targeting the hybrid FPGAs.

Hardware Reduction for Mealy UFSMs

The Chapter deals with optimization of logic circuits of hybrid FPGA-based Mealy FSMs. First of all, the models with two state registers are discussed. This approach allows removal of direct dependence among logical conditions and output functions of Mealy FSM. Next, the proposed design methods are presented. Some improvements are proposed for further hardware reduction. They are based on the special state assignment and transformation of state codes. The proposed methods target joint using such blocks as LUTs, PLAs and EMBs in FSM circuits. The models are discussed based on the principle of object transformation. The last part of the chapter is connected with design methods connected with the object transformation.

Code sharing in CPLD-based Moore FSMs

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with CPLDs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.

Designing HFPGA-based FSMs with counters

A method is proposed for hardware reduction of HFPGA-based Moore FMSs logic circuit. The method is based on replacement of state register by state counter. The counter can be increased during both conditional and unconditional transitions. There is an example of application of proposed method.

Encoding of chain outputs in FPGA-based Moore FSMs

A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The specific of the proposed method is that the counter content is incremented for unconditional and conditional transitions. An example of application of proposed method is given.