Larysa Titarenko

Logic Synthesis for FSM-Based Control Units

The control unit is one of the most important parts of any digital system responsible for interplay of other system blocks. Very often, the model of a finite state machine (FSM) is used to represent the behaviour of a control unit. Modern computer-aided design tools include a lot of optimal solutions (library cells) for implementation of such regular blocks of digital systems as decoders, multiplexers, parallel multibit adders and so on. But as a rule, control units have an irregular structure which makes impossible to design their logic circuits using the standard library cells. To use these cells, an FSM can be represented by a multilevel model based on the principle of structural decomposition. In multilevel models, for example, multiplexers are used to replace logical conditions, decoders are used to implement microoperations, and different memory blocks are used to transform object codes. Design methods depend strongly on such factors as an FSM model in use, specific features of logic elements implementing its logic circuit, characteristics of a control algorithm to be interpreted. In the case of Moore FSM, optimization methods are based on existence of the classes of pseudoequivalent states. Their use permits to compress the transition table of Moore FSM till the size of the table for equivalent Mealy FSM. In the case of Mealy FSM, optimization methods are based on transformation of either object codes, or interpreted graph-schemes of algorithm. In the case of CPLD, the hardware decrease can be achieved using more than single source of state codes. In the case of FPGA, the structural decomposition allows using embedded memory blocks for implementation of decoding logic. In case of ASIC, design methods target on minimization of the chip area occupied by an FSM circuit. It can be achieved due to use of different encoding methods, where both internal states and collections of microoperations can be encoded. If a control algorithm is a linear one, then a state register of Moore FSM can be replaced by a counter. It leads to simplification of the input memory functions and, in turns, to the hardware amount decrease. The book includes a lot of design methods targeted on logic synthesis of both Mealy and Moore FSMs, where their logic circuits can be implemented using ASIC, as well as CPLD or FPGA. The most of discussed methods belong to the authors of this book. This book will be interesting and useful for students and postgraduates in the area of Computer Science, as well as for designers of digital systems included complex control units. Proposed models and design methods open new possibilities for creating logic circuits of control units with optimal hardware amount.

Logic Synthesis for Compositional Microprogram Control Units

The control unit is one of the most important parts of any digital system. As a rule, control units have an irregular structure, which makes the processing of their logic circuits design very sophisticated. One possible way to optimise such characteristics as the size or performance of control units is to adapt their structures to the particular properties of interpreted control algorithms. In this book control algorithms are represented by the linear graph-schemes of algorithms (GSA), where the number of operator vertices is not less than 75% of the total number of all algorithm vertices. A special class of control units named as compositional microprogram control units (CMCU) is proposed as the best way for interpretation of linear control algorithms. The CMCU includes a finite state machine, which addresses microinstructions of interpreted microprogram, and a microprogram control unit including control memory, which keeps only microoperations of initial GSA. The microprogram control unit uses the principle of natural addressing of microinstructions. Organization of the control unit proposed in the book increases regularity of the circuit, because the system of microoperations is implemented using standard blocks, such as PROM or RAM. At the same time, an irregular part of the system described by means of Boolean functions is reduced. It permits a decrease in the total number of logical elements (PAL, GAL, PLA, FPGA) in comparison with other models of finite state machines. The main goal of all proposed methods is reduction of the number of field-programmable logic devices used for implementation of logic circuit of the addressing FSM. This book will be interesting and useful for students and postgraduates in the area of Computer Science and for designers of modern digital devices. Compositional microprogram control units enlarge the class of models applied for implementation of control units with modern field-programmable logic devices.

Synthesis and Optimization of FPGA-Based Systems

Part I Design of digital circuits and systems on the basis of FPGA.- Part II Methods for optimization of finite state machines for FPGA-based circuits and systems.

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

HARDWARE REDUCTION IN FPGA-BASED MOORE FSM

The methods are proposed targeting to reduce the numbers of both look-up table elements and embedded memory blocks in the logic circuit of a Moore finite state machine. The proposed methods are bas...

Control and Adaptation in Telecommunication Systems

PDF : Control And Adaptation In Telecommunication Systems: Mathematical Foundations (Lecture Notes In Electrical Engineering) By Vladimir Popovskij Doc : Control And Adaptation In Telecommunication Systems: Mathematical Foundations (Lecture Notes In Electrical Engineering) By Vladimir Popovskij ePub : Control And Adaptation In Telecommunication Systems: Mathematical Foundations (Lecture Notes In Electrical Engineering) By Vladimir Popovskij

Synthesis Of Compositional Microprogram Control Units With Sharing Codes And Address Decoder

The method of synthesis of compositional microprogram control units with sharing codes and address decoder is proposed. In comparison with traditional way of synthesis of control units with sharing codes, there is additional block (address decoder) implemented. Thanks to it proposed method permits to use the principle of sharing codes under any characteristics of operational linear chains of initial flow-chart

Optimization Of Control Memory Size Of Control Unit With Codes Sharing

The method of design of compositional microprogram control unit with codes sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair code of operational linear chain, code of components. Such approach permits to use all positive features of codes sharing independently on characteristics of interpreted flow-chart of algorithm. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given

Reduction in the number of LUT elements for control units with code sharing

Reduction in the number of LUT elements for control units with code sharing Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

Design of FPGA-based Moore FMSs with counters

Abstract A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on replacement of the state register by a state counter. The main di_erence form already known methods is that the counter increases its state during conditional and unconditional transitions. An example of application of proposed methods is given.