Jack J. H. Chen

Data path development for multiple electron beam maskless lithography

Electron beam lithography has been used in the production of integrated circuits for decades. However, due to the limitation of throughput it was not a viable solution for high volume manufacturing and its biggest application is the production of semiconductor masks. For many considerations it has particularly now become desirable to eliminate the semiconductor mask and introduce maskless lithography for semiconductor fabrication. Multiple Electron Beam Maskless Lithography (MEBML2) has been proposed as a solution to overcome the traditional source current limitation of an electron beam system by using many thousands of parallel electron beamlets to write a pattern directly on the wafer. In developing the MEBML2 tool the challenges have shifted and, in absence of the mask, the system data path has emerged as one of the central challenges. The main theme in the data path development is bandwidth. The required raw bandwidth at the patterning beams is determined by throughput and resolution, i.e. pixel size and number of intensity modulation levels. To achieve a production worthy throughput at 10 wafers per hour in a Gaussian-beam-based maskless lithography system, by writing 3.5-nm pixels at 2 levels (on/off) which is required for the 22-nm lithography node, the required aggregate bandwidth at the beam blanker array is up to 45 Tbit/s. Such a large bandwidth requirement means that the data path architecture is mainly characterized by the bandwidth of the data streams in the system. Compression techniques can be used to reduce the intermediate data stream bandwidth requirements and consequently lead to simplifying the system design, reducing power consumption and footprint, but come at the cost of increased data processing complexity and possible limitations on throughput. In this paper we will show results from the development of a prototype data path for the Gaussian-beam-based maskless lithography system. A new concept for data processing and storage is proposed. The vertex-based processing and storage technique is adopted to reduce memory usage considerably, with only modest requirements on the hardware resources. It reveals that a realistically implementable data path system for the maskless lithography tool in high volume manufacturing is feasible.

High throughput maskless lithography: low voltage versus high voltage

The beam energy is a driving design parameter for electron beam lithography systems. To be able to compare the differences of low kV (5 kV) and high kV (100 kV) for a high-throughput system the limitations of both types of systems are evaluated. First the effect on the CD uniformity and throughput is analyzed. For any shot noise limited system the dose that is needed to obtain a required CD uniformity can be calculated. This dose depends on the total spot size and the efficiency of the electrons in the resist. For a smaller spot less dose is required than for a large spot. The current in a single beam is also determined by the spot size. A larger spot has more current. With these parameters an optimization of the required dose, spot size and single beam current can be made. It is found that although for high kV it is easier to create a small spot with a high current the low resist-exposure efficiency of the high-energy electrons limits the throughput, because the required dose is large. It is also found that for 10 wafers per hour multiple lenses or columns are required. For practical reasons (a high kV lens cannot be made as small as a low kV lens) there is a clear preference for the use of low energy in high-throughput systems. Another aspect that is crucial in the lithography process is the overlay. One of the main differences between high and low energy systems is the power that is dissipated in the wafer and the resulting error due to expansion. It is found that for both energies wafer heating is an issue, but for low kV there seem to be solutions, while for high kV the problem is 30 times bigger.

Balancing lithographic performance and resist outgassing in EUV resists

Resolution (R), line-width roughness (L), and sensitivity (S) are three key indices describing the performance of a resist. When optimizing a resist to compromise the RLS trade-off in extreme-ultraviolet lithography, outgassing of the resist also needs to be considered, because it will cause deposition of cleanable and non-cleanable contaminants on the surface of the projection optics and reduce the throughput of the exposure tool. In this paper, the dependence of outgassing of a resist on its compositions, such as types of photo-acid generator, quencher, and acid liable group as well as their loadings are investigated systematically through a set of specially prepared resist samples. The outgassing of these samples is tested on EUVOM-9000 from Litho Tech Japan. The lithographic performances of these samples are also characterized on the ASML NXE3100. Directions for optimizing resist lithographic performance under the constraint of resist outgassing are proposed.

Future electron-beam lithography and implications on design and CAD tools

The steeply increasing price and difficulty of masks make the mask-based optical lithography, such as ArF immersion lithography and extreme ultra-violet lithography (EUVL), unaffordable when going beyond the 32-nm half-pitch (HP) node[1]. Electron beam direct writing (EBDW), so called maskless lithography (ML2), provides an ultimate resolution without jeopardy from masks, but the extremely low productivity of the traditional single beam systems made it very laborious for mass manufacturing after over 3 decades of development. Although electron beam lithography has been long used for mask writing, it is yet very slow and typically takes from hours to days to write a complete 6-inch high-end mask. Direct writing a 300-mm wafer definitely would take much longer. Considering production efficiency in the cleanroom, the throughput of lithography tools should be in the order of 10 wafers per hour (WPH) per square meter as compared to that of an ArF scanner. To achieve such a throughput per e-beam column requires an improvement of more than 3-order. Increasing the beam current in the conventional single beam system would induce the space charge effect and thus is not a solution. Several groups [2][3][4][5] have proposed different multiple electron beam maskless lithography (MEBML2) approaches, by multiplying either Gaussian beams, variable shape beams or by using cell projections, to increase the throughput. The maturing MEMS technology and electronic control technology enable precise control of more than ten thousands or even millions of electron beamlets, writing in parallel. Without the mask constraint, the exposure can be made by continuously scanning across the entire wafer diameter as long as the ultra-high speed data rate can be supported. Hence a much slower scan speed is required and therefore a small tool footprint is achievable. A MAPPER Pre-Alpha Tool, composed of a 110-beam 5-keV column and a 300-mm wafer stage within a vacuum chamber of 1.3×1.3m2 footprint, has been installed and operational for process development in the advanced Giga-Fab cleanroom environment. By sending the pre-treated optical data to the correspondent photodiode of each blanker, each beam writes its own features independently in raster scan mode. Resolution beyond 30-nm HP resolution for both C/H and L/S by using chemical amplified resist (CAR) has been demonstrated. Applying proper E-beam proximity corrections (EPC), a 20-nm node test circuit layout has been successfully patterned. The tool will be upgraded with a new Electron-Optics column containing 13,000 beamlets and each beamlet projecting 7×7 sub-beams to achieve 10 WPH of 32-nm HP node wafers by a single chamber. The achievement of high productivity MEBML2 needs not only the beams, but also the data preparation. For a 10-WPH MEBML2 tool, one wafer exposure is done in 6 minutes. However, the pre-treatments, for example logic operation and EPC, of the huge reticle field data file typically take a few days in present-day mask writing and therefore drastic speed enhancement is required to really gain the benefits of ML2 in cycle time and flexibility. In MAPPERs writing approach, the circuit layout in GDSII or OASIS format at sub-nm addressing grid, whose file size can be up to hundreds of Giga-Bytes after EPC, has to be pre-rasterized to a bitmap writing format of 3.5-nm grid, which file size of the simple 0 and 1 bitmap for a full-26mm×33mm reticle field becomes more than 10 Tera-Bytes(TB). Real-time data decompression in the data path of the tool is designed to avoid storage and transportation of the extremely huge files. In this presentation, several suggestions regarding design, EPC and CAD tools to best fit the nature and operation of MEBML2 in high volume manufacturing are made. Because of high resolution by the e-beam, the restricted design rules due to resolution limit of the optical lithography, especially those related to the double patterning techniques, can be removed. By considering the speed of data treatment, required storage, and computing resources inside the data path, some minor rules like on-pixel design may be recommended. Although contour-based EPC has been demonstrated to meet CD requirements [6][7], hybrid EPC accompanied with dose modulation has been proposed to further enhance the imaging contrast. Even though we will optimize the tool precision to eliminate most of the beam-to-beam CD and overlay errors, it is nevertheless safer to propose some methods to avoid the BtB stitching on critical devices.

Characteristics performance of production-worthy multiple e-beam maskless lithography

E-beam direct write (EBDW) is one of the potential solutions for technology nodes of 28-nm half-pitch (HP) and beyond. Throughput limitation confined its development mostly to small-volume prototyping. Recently, proposals have been made to achieve throughput greater than 10 wafers per hour (WPH) on a single column with >10,000 beams writing in parallel (MEBDW), or even greater than 100 WPH by further clustering multiple columns within a typical production-tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array driven by high-speed optical data path architecture to simultaneously control >10,000 beams, switching them on and off independently. The MAPPER Pre-Alpha Tool with a 110-beam, 5-keV column and a 300-mm wafer stage has been installed in a semiconductor manufacturing cleanroom environment and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 30-nm half-pitch (HP) dense hole on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including resolution, local variation, focusing, energy latitude, proximity effect correction and electron scattering model fitting of hole patterning are discussed. Similar to mask-error-enhanced-factor (MEEF), the new writing-error-enhanced-factor (WEEF) to describe the impact of writing error, is introduced.

An accurate method to determine the amount of out-of-band light in an EUV scanner

In this paper, we proposed a new design of the test mask to measure the amount of the out-of-band (OOB) light from an extreme-ultraviolet (EUV) light source by detuning the period of the multilayer (ML), rather than changing the material of the absorber, to suppress reflection of EUV light. The new OOB test mask also reflects essentially the same OOB light as that of the production mask at each wavelength in the whole OOB spectral range. With the help of the new OOB test mask, the contributions to the background intensity from in-band flare and OOB light can be correctly separated and an accurate optical-proximity-correction (OPC) model can be established.

Mitigation of image contrast loss due to mask-side non-telecentricity in an EUV scanner

Due to the use of reflective optics in extreme-ultraviolet lithography (EUVL), the chief ray angle of incidence at the object (mask) side (CRAO) cannot be zero. If the conventional resolution enhancement technique (RET) of off-axis illumination (OAI) is used, such mask-side non-telecentricity degrades aerial image contrast partly because of asymmetry (w.r.t. the mask) of the two beams in an incident beam pair and partly because of asymmetry (w.r.t. the mask) of the two diffraction orders of either incident beam. The former leads to intensity imbalance of the two incident beams (after leaving the mask) and the latter leads to amplitude and phase imbalance of the two diffraction orders of either incident beam. Solutions proposed previously only alleviate the former and have little help for the latter. In this paper, we introduce n=1 absorber to eliminate the phase imbalance so that the transverse shift between the two aerial images formed by the two incident beams can be minimized and the contrast of the final aerial image (by superposition of the two) can be restored.

Limitation of OAI + AttPSM in EUVL

In extreme ultraviolet lithography (EUVL), the application of off-axis illumination (OAI) leads to degradation in aerial image contrast, resulting in an unacceptably high mask error enhancement factor as the pattern pitch becomes smaller, even if an attenuated phase-shifting mask (AttPSM) of optimized attenuation is employed. We show that this is an intrinsic problem of OAI and cannot be remedied by adopting a thinner absorber, a smaller chief ray angle of incidence at the object side, or a projection optics box with a higher numerical aperture. Based on simulation results using the best conditions for OAI, we may conclude that single-patterning EUVL will probably end at a technology node with the minimum pitch of 22 nm, unless we can come up with other innovative ways for performing EUVL imaging or designing and formulating resists with blurs less than 5 nm at reasonable exposure dose.

Imaging performance of production-worthy multiple-E-beam maskless lithography

E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour (WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of beams, switching them on and off independently. The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including illumination, focusing, and CD uniformity, are discussed.

Quencher distribution engineering for out-of-band insensitive EUV resists: experiments and stochastic simulation

We investigated the effect of quencher type and loading concentration in OoB-insensitive EUV resists via actual exposure on the latest EUV scanner and stochastic simulation using Prolith. Model resist samples with two quencher types, conventional base type and photo-decomposable base type, at variant loading concentrations were prepared and tested. Basic indicators of lithographic performance, such as depth of focus, energy latitude, and line-width roughness were significantly improved by 80 nm, 8.4% and 25%, respectively along with a moderate increase of sensitivity (ca. 5mJ/cm2) under the optimized quencher condition. Meanwhile, we further quantitatively analysis the outgassing-induced contamination growth to realize the quencher distribution engineering effect on outgassing issue in EUV lithography. In addition, stochastic simulation for EUV resist featuring various types of quenchers provides certain correlation with the experimental results.