Jack Marlyn Mccreary

Enhancement of flip-chip fatigue life by encapsulation

Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin with a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of the resin along an edge of the chip. The encapsulant flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to obtain consistent flow under the chip without any bubbles is discussed. The filler size distribution and flow under the chip are shown in cross sections of several different materials, including low alpha emitting encapsulants for memory applications. Encapsulant formulations are tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges shows a five to ten times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4 joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service temperature ranges without conventional distance from neutral point (DNP) constraints. >

Flip-chip solder bump fatigue life enhanced by polymer encapsulation

Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin having a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low-CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of resin along an edge of the chip. The encapsulation flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to get consistent flow under the chip without any bubbles is discussed. The filler size distribution and flow under the chip are shown to cross sections of several different materials including low-alpha-emitting encapsulants for memory applications. Novel encapsulant formulations were tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges show a 5 to 10 times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4-joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service-temperature ranges without conventional DNP (distance from neural point) constraints.<<ETX>>

Flip-chip encapsulation on ceramic substrates

Flip-chip encapsulation has been shown to provide at least a 5-10/spl times/ improvement in fatigue life of C4 (controlled collapse chip connection) solder joints. IBM has developed, qualified and implemented encapsulation in production for a wide array of selected C4 footprint chips attached to ceramic substrates. In addition to providing a very substantial improvement in reliability, this technology has enabled major extensions to the flip-chip on ceramic menu by relaxing chip footprint or size constraints, accommodating larger chips and allowing smaller C4s on finer pitches. Also, new package technologies have evolved that feature thin and lightweight surface mountable designs that conform to industry outlines. IBM evaluated several encapsulant formulations and tested over 2000 encapsulated chips and 200000 individual C4s during the development and qualification phases. Test data was collected for a variety of accelerated thermal cycling (ATC) conditions and was supported by extensive finite element modeling. Chip configurations included memory and logic footprints and ranged in size to 14.7 mm chip size and 10.2 mm DNP (distance from neutral point of chip footprint). In all cases, ATC data showed a dramatic improvement in C4 life on encapsulated chips with no adverse effects in other tests. Several different encapsulant formulations, each with minor variations, were evaluated, and the encapsulant dispense and cure process was optimized for ease of manufacturing high production volumes that are required by IBM.<<ETX>>

Flip-chip soldering to bare copper circuits

The authors describe a process for providing high-yield/high-reliability C4 (controlled collapse chip connection) joining to bare copper circuitry. A study was undertaken in the course of implementing a major change in IBMs metallized ceramic (MC) and metallized ceramic-polyimide (MCP) production line. It involved joining chips with 95/5 Pb/Sn C4 solder bumps to bare copper pads on substrates to replace dip-tinned substrates with 90/10 pB/Sn-coated pads. An extensive analysis of the C4 interconnection was carried out. Over 30000 chips were joined to ceramic substrates to characterize wetting to the copper pads, evaluate C4 fatigue life, and assess any effect on reliability of natural and artificially induced defects in the C4 columns or wetted pad surface. C4 defect levels and C4 fatigue testing were equivalent for both types of product, tinned and untinned pads. Solder wetting to a clean copper surface was shown to be as good as wetting to a solder-coated surface. The reliability effect on the product due to partial wets was found to be insignificant. The technique for C4 interconnection joining to copper pads has been successfully implemented in many manufacturing sites. >