Jack O. Chu

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Strained Si NMOSFETs for high performance CMOS technology

Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.

Germanium channel MOSFETs: opportunities and challenges

This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-channel MOSFETs are discussed on the basis of our recent results. CMOS-compatible integration approaches of Ge channel devices are presented.

Influence of misfit dislocations on the surface morphology of Si1−xGex films

The influence of misfit dislocations on the surface morphology of partially strain relaxed Si1−xGex films is studied by atomic force microscopy and transmission electron microscopy. Surface steps arising from the formation of single and multiple 60° dislocations are identified. The role of such steps in the development of a cross‐hatch pattern in surface morphology is discussed.

Absolute rate constants for the reaction of silylene with hydrogen, silane, and disilane

Absolute rate constants for the reaction of silylene with hydrogen, silane, and disilane have been determined from direct time resolved measurements of silylene removal at room temperature. Silylene was generated and detected using laser resonance absorption flash kinetic spectroscopy. The rate constants are pressure dependent, consistent with expectations for the insertion reactions typical of silylene. The pressure dependence of the overall rate constants has been determined from 1 to 100 Torr for reaction with hydrogen and silane and from 1 to 10 Torr for reaction with disilane. The results for reaction with hydrogen and silane have been successfully modeled using RRKM theory and high pressure bimolecular rate constants have been extracted. The rate constants determined in this work are significantly (10–104 times) faster than those calculated from literature values for the Arrhenius parameters. These findings require a significant upward revision in the heat of formation of silylene, and may require m...

Controllable valley splitting in silicon quantum devices

Silicon has many attractive properties for quantum computing, and the quantum-dot architecture is appealing because of its controllability and scalability. However, the multiple valleys in the silicon conduction band are potentially a serious source of decoherence for spin-based quantum-dot qubits. Only when a large energy splits these valleys do we obtain well-defined and long-lived spin states appropriate for quantum computing. Here, we show that the small valley splittings observed in previous experiments on Si–SiGe heterostructures result from atomic steps at the quantum-well interface. Lateral confinement in a quantum point contact limits the electron wavefunctions to several steps, and enhances the valley splitting substantially, up to 1.5 meV. The combination of electrostatic and magnetic confinement produces a valley splitting larger than the spin splitting, which is controllable over a wide range. These results improve the outlook for realizing spin qubits with long coherence times in silicon-based devices.

Heteroepitaxial growth of Ge on (100) Si by ultrahigh vacuum, chemical vapor deposition

The heteroepitaxial growth of pure Ge films on (100) Si by an ultrahigh vacuum, chemical vapor deposition technique is reported for the first time. The growth mode is found to be critically dependent on the substrate temperature during deposition. Two temperature regimes for growth are observed. Between 300 and 375 °C, growth occurs in a two‐dimensional, layer‐by‐layer mode, with an activation energy of 1.46 eV. Above 375 °C, island formation is observed. In the low‐temperature regime the growth rate is controlled by a surface decomposition reaction, whereas in the high‐temperature regime the growth rate is controlled by diffusion and adsorption from the gas phase.

Germanium-on-SOI Infrared Detectors for Integrated Photonic Applications

An overview of recent results on high-speed germanium-on-silicon-on-insulator (Ge-on-SOI) photodetectors and their prospects for integrated optical interconnect applications are presented. The optical properties of Ge and SiGe alloys are described and a review of previous research on SOI and SiGe detectors is provided as a motivation for the Ge-on-SOI detector approach. The photodetector design is described, which consists of lateral alternating p- and n-type surface contacts on an epitaxial Ge absorbing layer grown on an ultrathin-SOI substrate. When operated at a bias voltage of -0.5 V, 10mumtimes10 mum devices have dark current Idark, of only ~10 nA, a value that is nearly independent of finger spacing S, between S=0.3mum and 1.3mum. Detectors with S=1.3mum have external quantum efficiencies eta, of 52% (38%) at lambda=895 nm (850 nm) with corresponding responsivities of 0.38 A/W (0.26 A/W). The wavelength-dependence of eta agrees fairly well with expectations, except at longer wavelengths, where Si up-diffusion into the Ge absorbing layer reduces the efficiency. Detectors with 10 mumtimes10 mum area and S=0.6mum have -3-dB bandwidths as high as 29 GHz, and can simultaneously achieve a bandwidth of 27 GHz with Idark=24 nA, at a bias of only -1 V, while maintaining high efficiency of eta=46%(33%), at lambda=895 nm (850 nm). Analysis of the finger spacing and area-dependence of the device speed indicates that the performance at large finger spacing is transit-time-limited, while at small finger spacing, RC delays limit the bandwidth. Methods to improve the device performance are presented, and it is shown that significant improvement in the speed and efficiency both at lambda=850 and 1300 nm can be expected by optimizing the layer structure design

Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding

N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.

Electron and hole mobility enhancement in strained SOI by wafer bonding

N- and p-MOSFETs have been fabricated in strained Si-on-SiGe-on-insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) has been demonstrated in SSOI MOSFETs. These mobility enhancements are commensurate with those reported for FETs fabricated on strained silicon on bulk SiGe substrates.