Kevin K. Chan

A silicon nanocrystals based memory

A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (≊5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2–0.4 V with read and write times less than 100’s of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.

Single charge and confinement effects in nano‐crystal memories

Use of nano‐crystals of silicon in close proximity (1.5–4.5 nm) of a transistor channel lead to structures with pronounced memory where effects due to discrete number of electrons, confinement‐induced subbands in inversion layers and discrete energy states in quantum dots, random charge distribution in quantum dots, and transmission through a strong barrier are very important. Experimental results show plateaus in threshold voltage at low temperatures, spaced nearly equally apart, and indicative of single electron effects. Varying the oxide thickness shows strong influence on speed and charge retention. We confirm the strength of confinement effects and discuss the underlying considerations in the operation of the memory that are related to the reduced volume, strength of the barrier, and random distribution of the trapped charge in nano‐crystals.

High performance CMOS fabricated on hybrid substrate with different crystal orientations

A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm.

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Volatile and non-volatile memories in silicon with nano-crystal storage

A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Hybrid-orientation technology (HOT): opportunities and challenges

At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO 2 gate dielectrics

Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.