Jacob Savir

Scan-based transition test

Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e., one-bit-shift) pattern in the scan chain. Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise if this strategy is used. Here, several issues of skewed-load transition test are investigated. Issues such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality are thoroughly studied. >

Skewed-Load Transition Test: Part I, Calculus

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs in principle when testing the combinational logic residing between scan chains. In the skewedload test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e. one bit-shift) pattern in the scan chain. This paper describes a calculus that allows one to compute the complete set of skewed-load transition test vectors. The calculus is capable of simultaneously computing both the first and second vector of the delay test pair. Probabilistic analysis of random pattern skewedload-based transition test is also discussed in this paper. We show how to extend both the ParkerMcCluskey algorithm and the cutting algorithm to compute detection probability of transition faults.

Random pattern testability of delay faults

La detection de chemins lents en logique combinatoire par des structures aleatoires est etudiee

Skewed-Load Transition Test: Part II, Coverage

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

Identification of failing tests with cycling registers

A method is presented of operating on signatures from a cycling register such that the complexity of identifying multiple failing tests is comparable to that of identifying a single failing test. The method has some interesting aliasing characteristics. The authors show the probability of aliasing and suggest how it can be kept relatively small. The efficiency of the method decreases as the number of failing tests increase. The reduction in efficiency is due to an increase in aliasing probability caused by footprints being lost in the cycling registers. The larger the number of failing tests, the greater is the chance that aliasing will occur.<<ETX>>

AT-SPEED TEST IS NOT NECESSARILY AN AC TEST

In many circles at-speed test is synonymous to AC test. The object of this paper is to root out this misconception. In order to achieve an effective AC test special attention must be paid to the way the patterns are generated. The AC strength is a measure that allows assessing how well a pattern generator can serve in applying AC test vectors to the logic. Generators with high AC strengths tend to perform better than generators with low AC strengths.

Test limitations of parametric faults in analog circuits

This paper investigates the detectability of parameter faults in linear, time-invariant, analog circuits and sheds new light on a number of very important test attributes. We show that there are inherent limitations with regard to analog faults detectability. It is shown that many parameter faults are undetectable irrespective of which test methodology is being used to catch them. It is also shown that, in many cases, the detectable minimum-size parameter fault is considerably larger than the normal parameter drift. Sometimes the minimum-size detectable fault is two to five times the parameter drift. We show that one of the fault-masking conditions in analog circuits, commonly believed to be true, is, in fact, untrue. We illustrate this with a simple counter example. We also show that, in analog circuits, it is possible for a fault-free parameter to mask an otherwise detectable parametric fault. We define the small-size parameter fault coverage, and describe ways to calculate or estimate it. This figure of merit is especially suitable in characterizing the test efficiency in the presence of small-size parameter faults. We further show that circuit specification requirements may be translated into parameter tolerance requirements. By doing so, a test for parametric faults can, indirectly, address circuit specification compliance. The test limitations of parametric faults in analog circuits are illustrated using numerous examples.

Reducing the MISR size

Multiple-input signature registers (MISRs) are commonly used in built-in self-test (BIST) applications. The size of the MISR is dictated by the number of signals it has to compress. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Large size MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of reducing the MISR so that it samples multiple signals at every stage. Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. This paper analyzes all these issues; shows ways to reduce their negative effect, and compares the results to previously published proposals.

Scan latch design for delay test

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.

Coefficient-based test of parametric faults in analog circuits

Coefficient-based test (CBT) is introduced for detecting parametric faults in analog circuits. The method uses pseudo Monte Carlo simulation and system-identification tools to determine whether a given circuit under test (CUT) is faulty. From the circuit description, and component tolerance specifications, the tolerance boxes of all circuit transfer-function coefficients are precomputed and used during the test. Using input/output signal information, the test procedure attempts to extract the CUTs transfer function. When this extraction is complete-if one or more of these measured transfer-function coefficients are found to be outside their tolerance boxes-the circuit is declared faulty.