Zhiqiang You

Logic Operation-Based DFT Method and 1R Memristive Crossbar March-like Test Algorithm

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0 s or not at a time. A March-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.

An adaptive neural network A/D converter based on CMOS/memristor hybrid design

A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems for its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model neural network based on CMOS/memristor hybrid design is proposed to perform the analog-to-digital conversion without oscillations. The circuit is composed of CMOS neurons and memristor synapses. The A/D converter (ADC) is trained by the least mean square (LMS) algorithm. The conductance of the memristors can be adjusted to convert input voltages with different ranges, which makes the ADC flexible. Using memristors as synapses in neuromorphic circuits can potentially offer high density.

A Parallel-SSHI Rectifier for Ultra-low-voltage Piezoelectric Vibration Energy Harvesting

An idling scheme of Synchronous Switch Harvesting on Inductor (SSHI) is proposed for piling up output voltage of the piezoelectric energy (PE) harvester cycle by cycle, to deal with the PE harvester’s low output voltage. The proposed rectifier integrates active diodes and a parallel-SSHI technique with a simple control scheme, and therefore has a high efficiency. The simulation results demonstrate the feasibility of proposed rectifier, which is able to extract energy from a ultra-low-voltage PE harvester.

A signal degradation reduction method for memristor ratioed logic (MRL) gates

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a study case. Compared to the previous MRL-based standard cell design, the proposed circuit can reduce 11.1% memristor cells, 22.2% CMOS transistors, 38.9% vias, 58% power. Compared to the previous MRL-based optimized design, the proposed design can reduce 11.1% memristor cells, 12.5% CMOS transistors, 98.1% power, 98.1% energy.

A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design

In this paper, we propose a comprehensive scheme that simultaneously achieves IP protection in both after-sale and evaluation periods. Our key idea is to build a pre-verification path into an active metering structure, with a non-functional defect purposely attached to the path, rendering any potential pirating users unwilling to risk the defective behavior of the fabricated chips. Using the MCNC’91 benchmarks, we achieve a large area-to-power ratio proving the feasibility of our scheme. At the same time, compared with a well-known metering scheme, the proposed scheme can significantly improve the robustness against brute-force attack, roughly by an average value of 2 per layer. The scheme can also reduce the area and power overhead by 4.4% and 11.2% on average considering an extra 5 to 10 layers.