Jacobo Valdes

The Recognition of Series Parallel Digraphs

We present a linear-time algorithm to recognize the class of vertex series-parallel (VSP) digraphs. Our method is based on the relationship between VSP digraphs and the class of edge series-parallel multidigraphs. As a byproduct of our analysis, we obtain efficient methods to compute the transitive closure and transitive reduction of VSP digraphs, and to test isomorphism of minimal VSP digraphs.

The recognition of Series Parallel digraphs

We present an algorithm that recognizes the class of General Series Parallel digraphs and runs in time proportional to the size of its input. To perform this recognition task it is necessary to compute the transitive reduction and transitive closure of any General Series Parallel digraph. Our analysis is based on the relationship between General Series Parallel digraphs and a class of well known models of electrical networks.

ALI: A Procedural Language to Describe VLSI Layouts

ALI is a procedural language to specify VLSI layouts. It allows the designer to describe layouts without reference to the sizes and positions of the layout elements or to the distances between them. Among the interesting characteristics of ALI are that it does not need design rule checking, is easy to extend, facilitates the division of labor and permits the easy update of a layout to new design rules or to new processes. The general features of the language and the experience gained with a preliminary implementation of it are described.

Recognition and Isomorphism of Two Dimensional Partial Orders

This paper presents an algorithm for recognizing two dimensional partial orders. The algorithm accepts as input an arbitrary partial order G and responds “yes” if the dimension of G is less than or equal to two and responds “no” otherwise. As part of the recognition process, the algorithm decomposes the partial order in a canonical way which can be used to determine whether two partial orders of dimension two are isomorphic. Both the recognition and the isomorphism algorithms can be implemented to run in time O(n2) when the input is a partial order on n elements. The best previously known algorithms for these two tasks had a worst case behavior of O(n3).

Prime subprogram parsing of a program

A parsing method based on the triconnected decomposition of a biconnected graph is presented. The parsing algorithm runs in linear time and handles a large class of flow graphs. The applications of this algorithm to flow analysis and to the automatic structuring of programs are discussed.

VLSI Layout as Programming

In th i s pape r we descr ibe a ve ry i m p o r t a n t c o m p o n e n t of a n y VLSI (very largescale in t eg ra t ion ) des ign e n v i r o n m e n t : a tool to a u t o m a t e the l a y o u t of circuits . Th i s work is p a r t of a n effort to c rea te a n i n t e g r a t e d e n v i r o n m e n t for VLSI des ign ( including l ayou t sys tems, device a n d swi tchlevel s imula tors , a n d t e s t ing facilities} cu r r en t ly u n d e r way a t P r i n c e t o n Univers i ty .

Census functions: An approach to VLSI upper bounds

A model of VLSI computation suitable for the description of algorithms at a high level is introduced. The model is basically a language to express parallel computations which can be efficiently implemented by a VLSI circuit. This language is used to describe area-time efficient algorithms for a few well known graph problems. The exact complexity of these algorithms and their relevance to recent work on the inherent limitations of VLSI computations are also presented.

Programming aspects of VLSI: (preliminary version)

Two components of a VLSI design environment being built at Princeton are described. The general theme of this effort is to make the design of VLSI circuits as similar to programming as possible. A conscious attempt is being made to apply experience in the design of large software systems to the creation of an appropriate environment for VLSI circuits. The two components described are a procedural language to specify circuit layouts and a switch-level circuit simulator for layout produced with this language. They have been chosen for presentation because many issues in their design are very similar to the issues that arise in the design of programming languages and software environments.