Jacques-Olivier Klein

Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Perpendicular-magnetic-anisotropy CoFeB racetrack memory

Current-induced domain wall motion in magnetic nanowires drives the invention of a novel ultra-dense non-volatile storage device, called “racetrack memory.” Combining with magnetic tunnel junctions write and read heads, CMOS integrability and fast data access speed can also be achieved. Recent experimental progress showed that perpendicular-magnetic anisotropy (PMA) CoFeB could be a good candidate to build up racetrack memory and promise high performance like high-density (e.g., ∼1 F2/bit), fast-speed, and low-power beyond classical spin transfer torque memories. In this paper, we first present the design of PMA CoFeB racetrack memory and a spice-compatible model to perform mixed simulation with CMOS circuits. Its area, speed, and power dissipation performance has been simulated and evaluated based on different technology nodes.

Robust neural logic block (NLB) based on memristor crossbar array

Neural networks are considered as promising candidates for implementing functions in memristor crossbar array with high tolerance to device defects and variations. Based on such arrays, Neural Logic Blocks (NLB) with learning capability can be built to replace Configurable Logic Block (CLB) in programmable logic circuits. In this article, we describe a neural learning method to implement Boolean functions in memristor NLB. By using Monte-Carlo simulation, we demonstrate its high robustness against most important device defects and variations, like static defects and memristor voltage threshold variability.

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems

Spin-transfer torque magnetic memory (STT-MRAM) is currently under intense academic and industrial development, since it features non-volatility, high write and read speed and high endurance. In this work, we show that when used in a non-conventional regime, it can additionally act as a stochastic memristive device, appropriate to implement a “synaptic” function. We introduce basic concepts relating to spin-transfer torque magnetic tunnel junction (STT-MTJ, the STT-MRAM cell) behavior and its possible use to implement learning-capable synapses. Three programming regimes (low, intermediate and high current) are identified and compared. System-level simulations on a task of vehicle counting highlight the potential of the technology for learning systems. Monte Carlo simulations show its robustness to device variations. The simulations also allow comparing system operation when the different programming regimes of STT-MTJs are used. In comparison to the high and low current regimes, the intermediate current regime allows minimization of energy consumption, while retaining a high robustness to device variations. These results open the way for unexplored applications of STT-MTJs in robust, low power, cognitive-type systems.

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes.

Design considerations and strategies for high-reliable STT-MRAM

Abstract Benefiting from Spin Transfer Torque (STT) switching approach, second generation of Magnetic RAM (MRAM) promises low power, great miniaturization prospective (

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I > Ico) and Neel-Brown model (I <; 0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication.

A High-Reliability, Low-Power Magnetic Full Adder

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area.

Self-Enabled “Error-Free” Switching Circuit for Spin Transfer Torque MRAM and Logic

Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g., <; 100 μA at 65 nm), simple switching scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate, which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing “error-free” as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area, power, and speed performance.

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology

Conventional MOS integrated circuits and systems suffer serve power and scalability challenges as technology nodes scale into ultra-deep-micron technology nodes (e.g., below 40nm). Both static and dynamic power dissipations are increasing, caused mainly by the intrinsic leakage currents and large data traffic. Alternative approaches beyond charge-only-based electronics, and in particular, spin-based devices, show promising potential to overcome these issues by adding the spin freedom of electrons to electronic circuits. Spintronics provides data non-volatility, fast data access, and low-power operation, and has now become a hot topic in both academia and industry for achieving ultra-low-power circuits and systems. The ITRS report on emerging research devices identified the magnetic tunnel junction (MTJ) nanopillar (one of the Spintronics nanodevices) as one of the most promising technologies to be part of future micro-electronic circuits. In this review we will give an overview of the status and prospects of spin-based devices and circuits that are currently under intense investigation and development across the world, and address particularly their merits and challenges for practical applications. We will also show that, with a rapid development of Spintronics, some novel computing architectures and paradigms beyond classic Von-Neumann architecture have recently been emerging for next-generation ultra-low-power circuits and systems.