Jae Hak Lee

Pre-bonding method using self-alignment effect for multichip packaging

An efficient C2C/C2W oxide bonding technique using self-alignment effect of a pair of hydrophilic chip surfaces, which are activated by plasma, is applied to 3D stacking of multichip packaging in this work. Self-alignment and pre-bonding technique can provide high-speed bonding process and high-precision chip alignment accuracy simultaneously without high-precision chip manipulator. Through experiments, we could acquire high hydrophilic silicon surfaces using plasma surface activation and measured position errors and rotational error of aligned chips is smaller than 5µm and 0.04 degrees respectively because of self-alignment effect between hydrophilic surfaces of chips. In addition, temporary bonding is formed successfully by secondary bonding between silanol groups (Si-OH) on the hydrophilic silicon chip surfaces when the DI water is evaporated by heating, which prevents contamination of bonding surface and helps of manipulation of multi-stacked chips easily.

Design of Cylinder Horn for Ultrasonic Welding

The cylinder horn is designed to increase uniformity of the displacement on the output face through simulation and experiments for the simple cylinder, spool and step horns. The modal analysis is conducted numerically to calculate the vibration mode and stress distribution of the cylinder horn, and the design of experiment (DOE) technique is employed to determine the optimum configuration of the spool horn. Displacement of the cylinder horn was measured using the Laser Doppler Vibrometer (LDV), and experimental results show good agreements with the predicted results. It appears that uniformity higher than 95% can be achieved with the spool horn when the proper dimension of the groove is used.

A study on wafer level TSV build-up integration method

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.

Novel sidewall interconnection using perpendicular circuit die with non-solder bumps for 3D chip stack

A new sidewall interconnection using perpendicular circuit die is implemented in this work; this device can be applied to fabrication of chip stacks. Experiments were conducted by stacking four chips each having a thickness of 200μm; the configuration of the pad on the test chip is similar to that of a memory chip. The chips for stacking were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding using a perpendicular circuit die. The interconnection quality of the chip stack was examined through SEM images. The images show that the interconnections were made successfully. A high-temperature/high-humidity test was conducted on the stacked chip. A high-temperature/high-humidity test at 85°/85%RH lasting 1000 hours was used to investigate the mechanical reliability of the packages. It was found that the stacked chips maintained their mechanical integrity. The bonding strength at all of the interfaces remained as high as they were before the test. The electrical resistance of the interconnection is comparable to that obtained using the wire bonding.

Novel Sidewall Interconnection Using a Perpendicular Circuit Die for 3-D Chip Stacking

A new sidewall interconnection approach using a perpendicular circuit die is implemented in this paper; this device can be applied to the fabrication of chip stacks. Thermal stress analysis is implemented using the ABAQUS software package to investigate the reliability issues of a stacked chip. The analysis indicates that it has little effect on the reliability of the stacked chip. Experiments were conducted by stacking four chips each having a thickness of 180 μm; the configuration of the pads on the test chip is similar to that of a memory chip. The stacked chips were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding a perpendicular circuit die on an edge of the chip stack. The interconnection quality of the stacked chip was examined through 3-D images obtained via Computed Tomography (CT) and X-ray imagery. The images show that the interconnections were made successfully. The electrical contact resistance of the interconnection is comparable with that obtained using the wire bonding.

High reliability insert-bump bonding process for 3D integration

3D packaging technologies using TSV (Through-Silicon Via) has been studied widely in the recent years to achieve higher packaging density, lower power consumption and higher electrical performance because electrical line is shorter and Cu TSV has smaller electrical resistivity than any other package. However, there are many technical issues such as thin wafer/chip handling, TSV electrical and mechanical reliability due to Cu metal, inspection and bonding process for multi-stacking to commercialize this package. Especially, bonding process is key technology to increase yield. To stack chips vertically, reliable and robust bonding technique is required because multi-stacking chips causes misalignment between chips during bonding process and thermal stress is induced by thermal cycle. Cu pillar bump bonding process is usually used to interconnect chips vertically although back-side and front-side bumping process is needed and also has weak shape to mechanical stress such as thermal stress. In this work, we suggested Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. ISB bonding process could simplify bonding process compared to Cu pillar bonding because it uses recessed Cu nail bump, which is formed by RIE process of back-side opened TSV and Sn planar bump, which is fabricated by CMP (Chemical-Mechanical Polishing) process of electroplated Sn layer without lithography to pattern bumps. Additionally, ISB bonding process has advantage of higher bonding strength and easier alignment between chips because Cu nail bump is interlocked mechanically within Sn planar bump and this design of bumps helps to align chips easier. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluated fluxing and no-fluxing cases. Although no-fluxing bonding process was applied to ISB bonding process, we could accomplish good bonding interface at 270°C due to oxide layer breakage effects.

Fault Diagnosis of VCM Type AF Actuator Module for Phone Camera by Vibration Analysis

A voice coil motor (VCM) is the module to realize auto-focus function in mobile devices such as smartphones and tablet PCs. The VCM has very complicated structure in a small dimension. There are many faults like large hysteresis, short movement range and improper starting current. However, VCM makers are struggling to point out the cause of faults. Break-down analysis is also difficult to apply because main VCM parts are tightly bonded together and easily deformable during disassembly processes. Therefore, we proposed the novel diagnosis method of VCM faults without breaking it. Our method expected to classify the causes of faults by analyzing vibration characteristics of VCMs. Frequency spectrum characteristics and fast Fourier transform (FFT) spectrum analysis are performed. Experimental results revealed that natural frequency shifts shown for NG samples compare to good ones and the fluctuation of magnitude over natural frequency range appeared. Also, sidebands are observed in adjacent of integer multiple harmonic peaks for NG sample. We can find clear vibration characteristic differences caused by VCM defects. Therefore, the causes of defects expected to be classified and corresponding actions can be done in the production line that lead to high productivity of high quality VCM.

A study on the edge traces technique for 3D stack chip

An edge traces technique in the wafer level is proposed and implemented in this work, which can be applied to the fabrication of the stack chip. Experiments were conducted by stacking four test chips 100μm thick, and the configuration of the pad is based on the memory chip from the electronics company. The chips for stacking were fabricated successfully through dicing the wafer and curing the adhesives in the trench. When four chips were built up and metallized, the stack chip was 430f/m high, which is comparable to that of the TSV. The electrical resistance of the interconnection was measured to be 5Ω, which can be improved further with modification. The interconnection quality of the stack chip was examined through 3D images obtained with the use of the CT and X-ray. The images showed that the interconnections were made successfully.

Wafer level build-up stacking process using molten metal filling for multi-chip packaging

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments.

High temperature reliability of Pd-alloyed Au wire/Al bonding interface

Palladium (Pd) is an important alloying element of Au bonding wire which plays as solid solution-type alloying effect in Au matrix. The behavior of Pd at Au/Al bonding interface during the thermal aging, and its effect on Au/Al interfacial reactions were investigated. Two types of Pd-alloyed Au wires, Au-0.25wt%Pd (Low-Pd-Au wire: LP-wire) and Au-0.95wt%Pd (High-Pd-Au wire: HP-wire), were used for the fabrication of wire-bonded test vehicles (TVs). The TVs were thermally aged at 175°C up to 1200hours, and the formation of a ‘Pd-rich’ layer was investigated at Au-Al bonding interface by using a cross-sectional scanning electron microscope (SEM) and an electron probe microanalysis (EPMA). The ‘Pd-rich’ layer was confirmed only at the TVs fabricated with the HP-wire. According the results of a transmission electron microscope (TEM), the thickness of ‘Pd-rich’ layer was about 500nm and it located between HP-wire and Au8Al3 intermetallic compound (IMC) layer. Au4Al IMC did not detected in HP-wire TVs. In LP-wire TVs, we could not observe the ‘Pd-rich’ layer at bonding interface but Au4Al formed at the interface of LP-wire and Au8Al3 IMC. After long-term thermal aging, the bonding interface was degraded by the oxidation phenomena. According to the cross-section analysis, it was mainly due to the oxidation of Au4Al IMC and, therefore, the Au-Al bonding interface becomes vulnerable to this kind oxidation.