Tae Ho Ha

Pre-bonding method using self-alignment effect for multichip packaging

An efficient C2C/C2W oxide bonding technique using self-alignment effect of a pair of hydrophilic chip surfaces, which are activated by plasma, is applied to 3D stacking of multichip packaging in this work. Self-alignment and pre-bonding technique can provide high-speed bonding process and high-precision chip alignment accuracy simultaneously without high-precision chip manipulator. Through experiments, we could acquire high hydrophilic silicon surfaces using plasma surface activation and measured position errors and rotational error of aligned chips is smaller than 5µm and 0.04 degrees respectively because of self-alignment effect between hydrophilic surfaces of chips. In addition, temporary bonding is formed successfully by secondary bonding between silanol groups (Si-OH) on the hydrophilic silicon chip surfaces when the DI water is evaporated by heating, which prevents contamination of bonding surface and helps of manipulation of multi-stacked chips easily.

A study on wafer level TSV build-up integration method

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.

Automatic Combination & Assembly System for Phone Camera Lens Module

An automatic combination and assembly system for phone-camera lens modules was developed. The system enables the assembly of the relative orientation of the individual lenses making up the lens module. Conventional assembly systems assemble a lens module from eight assembly units. The developed system reduces this number to half by combining each lens and a spacer into a single assembly unit. Also, the number of transfer stages for sequential assembly is minimized without increasing the assembly time. Therefore, high productivity and a footprint that is only about 25 % of that of a conventional assembly system can be realized. The system features a modular design to allow it to cope with rapid changes in the market. Only a few components, such as the picker and guide, need to be replaced for changing to a new assembly model. § 이 논문은 대한기계학회 IT융합부문 2013년도 춘계학술대회 (2013. 5. 9.-10., 대명리조트) 발표논문임. † Corresponding Author, sjy658@kimm.re.kr C 2014 The Korean Society of Mechanical Engineers 송준엽 ∙ 하태호 ∙ 이창우 ∙ 김동훈 ∙ 전 종 220 화되며 소정의 성능을 확보하기 위해서는 단렌즈의 특성을 고려한 조립이 중요하게 되어 렌즈 방향성에 대한 고려가 필수적이다. 본 논문에서는 유동해석을 통하여 보압 및 냉각 온도와 같은 렌즈의 사출조건에 따른 광학적 특성 의 상관관계를 조사하였다. 또한, 사출렌즈의 방향 성을 제고하고 최적의 조합성을 탐색하여 이를 반 영한 렌즈모듈 조립이 가능한 렌즈 조합 시스템을

Bonding head design for thin wafer

In this paper, porous vacuum picker and bonding head to impose uniform pressure on all the surface of wafer in the bonding process are proposed newly. Porous vacuum picker could reduce deformation and warpage problem during handling thin wafer because it has many number of small vacuum hole which induce small vacuum pressure at those holes region. Also, to impose uniform pressure on the wafer under bonding process, bonding head is designed using air piston type with metal ball joint, which automatically compensate for coplanarity problem of bonding pad. FEM analysis and experiments are conducted to evaluate the performance of porous vacuum picker and bonding head of air piston type.

Embedded Controller Technology of Injection Molding Machine for Control and Monitoring

In this study, we introduce how to apply “Information and Communication Technology (ICT) to injection molding system. We report the current state of IT technology applied to produce their products in micro lens injection molding system. And we explain key technology of ICT for injection molding system and how to implement. Especially, we also mention about an embedded controller, also called as “M2M device”. It provides programmable intelligent functions, communication, various interfaces, amplifier functions and mobile device connection to our application.

High reliability insert-bump bonding process for 3D integration

3D packaging technologies using TSV (Through-Silicon Via) has been studied widely in the recent years to achieve higher packaging density, lower power consumption and higher electrical performance because electrical line is shorter and Cu TSV has smaller electrical resistivity than any other package. However, there are many technical issues such as thin wafer/chip handling, TSV electrical and mechanical reliability due to Cu metal, inspection and bonding process for multi-stacking to commercialize this package. Especially, bonding process is key technology to increase yield. To stack chips vertically, reliable and robust bonding technique is required because multi-stacking chips causes misalignment between chips during bonding process and thermal stress is induced by thermal cycle. Cu pillar bump bonding process is usually used to interconnect chips vertically although back-side and front-side bumping process is needed and also has weak shape to mechanical stress such as thermal stress. In this work, we suggested Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. ISB bonding process could simplify bonding process compared to Cu pillar bonding because it uses recessed Cu nail bump, which is formed by RIE process of back-side opened TSV and Sn planar bump, which is fabricated by CMP (Chemical-Mechanical Polishing) process of electroplated Sn layer without lithography to pattern bumps. Additionally, ISB bonding process has advantage of higher bonding strength and easier alignment between chips because Cu nail bump is interlocked mechanically within Sn planar bump and this design of bumps helps to align chips easier. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluated fluxing and no-fluxing cases. Although no-fluxing bonding process was applied to ISB bonding process, we could accomplish good bonding interface at 270°C due to oxide layer breakage effects.

Fault Diagnosis of VCM Type AF Actuator Module for Phone Camera by Vibration Analysis

A voice coil motor (VCM) is the module to realize auto-focus function in mobile devices such as smartphones and tablet PCs. The VCM has very complicated structure in a small dimension. There are many faults like large hysteresis, short movement range and improper starting current. However, VCM makers are struggling to point out the cause of faults. Break-down analysis is also difficult to apply because main VCM parts are tightly bonded together and easily deformable during disassembly processes. Therefore, we proposed the novel diagnosis method of VCM faults without breaking it. Our method expected to classify the causes of faults by analyzing vibration characteristics of VCMs. Frequency spectrum characteristics and fast Fourier transform (FFT) spectrum analysis are performed. Experimental results revealed that natural frequency shifts shown for NG samples compare to good ones and the fluctuation of magnitude over natural frequency range appeared. Also, sidebands are observed in adjacent of integer multiple harmonic peaks for NG sample. We can find clear vibration characteristic differences caused by VCM defects. Therefore, the causes of defects expected to be classified and corresponding actions can be done in the production line that lead to high productivity of high quality VCM.

Wafer level build-up stacking process using molten metal filling for multi-chip packaging

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments.

Study on Insert-Bump bonding process for multi-chip package

3D packaging technologies using TSV (Through-Silicon Via) has been studied widely in the recent years to achieve higher packaging density, lower power consumption and higher electrical performance because electrical line is shorter and Cu TSV has smaller electrical resistivity than any other package. However, there are many technical issues such as thin wafer/chip handling, TSV electrical and mechanical reliability due to Cu metal, inspection and bonding process for multi-stacking to commercialize this package. Especially, bonding process is key technology to increase yield. To stack chips vertically, reliable and robust bonding technique is required because multi-stacking chips causes misalignment between chips during bonding process and thermal stress is induced by thermal cycle. Cu pillar bump bonding process is usually used to interconnect chips vertically although backside and front-side bumping process is needed and also has weak shape to mechanical stress such as thermal stress. In this work, we suggested Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. ISB bonding process could simplify bonding process compared to Cu pillar bonding because it uses recessed Cu nail bump, which is formed by RIE process of back-side opened TSV and Planar Sn/3Ag pool-planar bump, which is fabricated by CMP(Chemical-Mechanical Polishing) process of electroplated Sn-3Ag layer without lithography to pattern bumps. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluated fluxing and no-fluxing cases. Although no-fluxing bonding process was applied to ISB bonding process, we could accomplish good bonding interface at 250°C due to oxide layer breakage effects.

Low temperature hybrid bonding using self-alignment

An efficient C2C/C2W oxide bonding technique using self-alignment effect of a pair of hydrophilic chip surfaces, which are activated by atmospheric plasma, is applied to 3D stacking of multichip package in this work. Self-alignment and pre-bonding technique can provide high-speed bonding process and high-precision chip alignment accuracy simultaneously without high-precision chip manipulator. Conventional Cu to Cu bonding requires high bonding temperature above 400 °C to get high bonding interface energy and form perfect bonding interface. In order to reduce bonding temperature, plasma activated oxide bonding and metal bonding simultaneously is applied, which is called as low temperature hybrid bonding. In addition, atmospheric N2 plasma is used to form hydrophilic surface and reduce bonding temperature because atmospheric N2 plasma shortens bonding process time compared to vacuum plasma. Contact angle variation is investigated according to gas concentration, voltage and time. Bonding interface energy is measured using 4 point bending method with respect to bonding temperature experimentally. Through experiments, we could acquire high bonding interface energy of 10.69J/m2 at 200°C.