Jae-Mo Koo

Measurements and modeling of two-phase flow in microchannels with nearly constant heat flux boundary conditions

Two-phase forced convective flow in microchannels is promising for the cooling of integrated circuits. There has been limited research on boiling flow in channels with dimensions below 100 /spl mu/m, in which bubble formation and flow regimes can differ from those in larger channels. This work develops single and multi-channel experimental structures using plasma-etched silicon with pyrex glass cover, which allow uniform heating and spatially-resolved thermometry and provide optical access for visualization of boiling regimes. Boiling was observed with less than 5/spl deg/C of super-heating in rectangular channels with hydraulic diameters between 25 and 60 /spl mu/m. The channel wall widths are below 350 /spl mu/m, which minimizes solid conduction and reduces variations in the heat flux boundary condition. Pressure drop and wall temperature distribution data are consistent with predictions accounting for solid conduction and homogeneous two-phase convection.

Closed-loop electroosmotic microchannel cooling system for VLSI circuits

The increasing heat generation rates in VLSI circuits motivate research on compact cooling technologies with low thermal resistance. This paper develops a closed-loop two-phase microchannel cooling system using electroosmotic pumping for the working fluid. The design, fabrication, and open-loop performance of the heat exchanger and pump are summarized. The silicon heat exchanger, which attaches to the test chip (1 cm/sup 2/), achieves junction-fluid resistance near 0.1 K/W using 40 plasma-etched channels with hydraulic diameter of 100 /spl mu/m. The electroosmotic pump, made of an ultrafine porous glass frit with working volume of 1.4 cm/sup 3/, achieves maximum backpressure and flowrate of 160 kPa and 7 ml/min, respectively, using 1 mM buffered de-ionized water as working fluid. The closed-loop system removes 38 W with pump power of 2 W and junction-ambient thermal resistance near 2.5 K/W. Further research is expected to strongly reduce the thermal resistance for a given heating power by optimizing the saturation temperature, increasing the pump flowrate, eliminating the thermal grease, and optimizing the heat exchanger dimensions.

Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures

The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory

Micromachined jets for liquid impingement cooling of VLSI chips

Two-phase microjet impingement cooling is a potential solution for removing heat from high-power VLSI chips. Arrays of microjets promise to achieve more uniform chip temperatures and very high heat transfer coefficients. This paper presents the design and fabrication of single-jets and multijet arrays with circular orifice diameters ranging from 40 to 76 /spl mu/m, as well as integrated heater and temperature sensor test devices. The performance of the microjet heat sinks is studied using the integrated heater device as well as an industry standard 1 cm/sup 2/ thermal test chip. For single-phase, the silicon temperature distribution data are consistent with a model accounting for silicon conduction and fluid advection using convection coefficients in the range from 0.072 to 4.4 W/cm/sup 2/K. For two-phase, the experimental results show a heat removal of up to 90 W on a 1 cm/sup 2/ heated area using a four-jet array with 76 /spl mu/m diameter orifices at a flowrate of 8 ml/min with a temperature rise of 100/spl deg/C. The data indicate convection coefficients are not significantly different from coefficients for pool boiling, which motivates future work on optimizing flowrates and flow regimes. These microjet heat sinks are intended for eventual integration into a closed-loop electroosmotically pumped cooling system.

Modeling of two-phase microchannel heat sinks for VLSI chips

Microchannel heat sinks with forced convective boiling can satisfy the increasing heat removal requirements of VLSI chips. But little is known about two-phase boiling flow in channels with cross-sectional dimensions below 100 /spl mu/m. This work develops and experimentally verifies microchannel simulations, which relate the temperature field to the applied power and flowrate. The simulations consider silicon conduction and assume an immediate transition to homogeneous misty flow, without the bubbly and plug-flow regimes in larger channels. Pressure drop and wall temperature predictions are consistent with data for a channel with cross-sectional dimensions of 50 /spl mu/m/spl times/70 /spl mu/m. The simulations explore the performance of a novel heat sink system with an electrokinetic pump for the liquid phase, which provides 1 atm and 15 ml/min. A temperature rise below 40 K is predicted for a 200 W heat sink for a 25 mm/spl times/25 mm chip.

Experimental study on two-phase heat transfer in microchannel heat sinks with hotspots

Hotspots, imposed by spatially non-uniform heat flux in a high performance circuit, increase the chip maximum junction temperature, which degrades the reliability and performance of electronic equipment. Microchannel heat sinks with two-phase convective heat transfer are effective for removing high heat flux exceeding 100 W/cm/sup 2/. Cross-linking of microchannels can be promising for achieving better temperature uniformity and more effective cooling due to the lateral fluid transport and mixing. This study experimentally investigates the impact of mass flow distribution on the chip temperature field in a multi-channel heat sink. Furthermore, the performance of two microchannel heat sinks is compared with different configurations: a regular microchannel heat sink and a cross-linked microchannel heat sink.

Study of Boiling Regimes and Transient Signal Measurements in Microchannels

Two-phase microchannel heat exchangers can achieve very large heat removal rate due to the phase change of the coolant. However, the design of two-phase microchannel heat exchangers has not yet considered the change of boiling regimes in microchannels under 150 µm, while the boiling regime has significant impact on convective heat transfer coefficient. This paper presents our study of boiling regimes in these microchannels as well as the transient pressure fluctuation caused by nucleation. These results will provide quantitative information to others designing small-diameter parallel channel heat exchangers.

Two-phase microchannel heat sinks for an electrokinetic VLSI chip cooling system

The trend towards higher speed and greater integration of modern ICs requires improved cooling technology. This paper describes the design and characterization of a two-phase microchannel heat sink in an electrokinetic VLSI chip cooling system. The heat sink achieves a thermal resistance of 1 K/W for a 1.2 cm/spl times/1.2 cm silicon thermal test chip under open-loop operation with a water flow-rate of 5 ml/min. Preliminary tests show that a closed-loop EK-pumped system running at 1.2 ml/min and 12 psi removes 17.3 W, with heat rejection at an aluminum fin array. Further optimization of the microchannel dimensions and the working fluid operating pressure are expected to lower the resistance below 0.25 K/W.

Enhanced nucleate boiling in microchannels

This paper studies the nucleate boiling conditions and mechanisms in plasma etched silicon microchannels below 150 /spl mu/m hydraulic diameter. Boiling regimes and the wall superheat in microchannels with various DI water surface tensions and wall surface roughness are discussed. The experiments show that wall superheat in microchannels is primarily due to the lack of active nucleation sites rather than limited channel space or a high liquid surface tension. By creating small cavities in the channel walls, superheat can be eliminated from as small as 28 /spl mu/m hydraulic diameter silicon channels.

Two-phase microfluidics for semiconductor circuits and fuel cells

Industrial trends are presenting major challenges and opportunities for research on two-phase flows in microchannels. Semiconductor companies are developing 3D circuits for which multilevel microfluidic cooling is important. Gas delivery microchannels are promising for PEM fuel cells in portable electronics. However, data and modeling are needed for flow regime stability, liquid entrainment/clogging, and bubble inception/departure in complex 2D and 3D geometries. This paper provides an overview of the Stanford two-phase microfluidics program, with a focus on recent experimental and theoretical progress. Microfabrication technologies are used to distribute heaters, thermometers, pressure sensors, and liquid injection ports along the flow path. Liquid PIV quantifies forces on bubbles, and fluorescence imaging detects flow shapes and liquid volume fraction. Separated flow models account for conjugate conduction, liquid injection, evaporation, and a variety of flow regimes. This work benefits strongly from interactions with semiconductor and fuel cell companies seeking validated models for product design.