Jae-Sung Kong

An artificial retina chip using switch-selective resistive network for intelligent sensor systems

We designed and fabricated a bio-inspired CMOS vision chip for edge detection using a switch-selective resistive network. A CMOS buffer circuit, which is embodied in the structure of a common drain amplifier, is commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive network, the total number of MOSFETs in the unit pixel and fixed-pattern noise (FPN) was reduced. In addition, by applying the saturating resistive network, the chip outputs a uniform edge signal under various lighting conditions. From the experimental results of a fabricated one-dimensional array with 20 pixels, we could confirm the operation of the vision chip.

Vision chip for edge detection with a function of pixel FPN reduction

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

Dynamic range extension of the n-well/gate-tied PMOSFET-type photodetector with a built-in transfer gate

We have designed and fabricated an active pixel sensor(APS) using an optimized n-well/gate-tied p-channel metal oxide semiconductor field effect transistor(PMOSFET)-type photodetector with a built-in transfer gate. This photodetector has a floating gate connected to n-well and a built-in transfer gate. The photodetector has been optimized by changing the length of the transfer gate. The APS has been fabricated using a 0.35 standard complementary metal oxide semiconductor(CMOS) process. It was confirmed that the proposed APS has a wider dynamic range than the APS using the previously proposed photodetector and a higher sensitivity than the conventional APS using a p-n junction photodiode.

Operation of a wide dynamic range CMOS image sensor based on dual sampling mechanism and its SPICE simulation

In this paper, a dynamic range(DR) extension technique based on a 3-transistor active pixel sensor(APS) and dual image sampling is proposed. The feature of the proposed APS is that the APS uses two or more photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. Compared with previously proposed wide DR(WDR) APS, the proposed approach has several advantages, such as no-external equipments or signal processing, no-additional time-requirement for additional charge accumulation, simple operation and adjustable DR extension by controlling parasitic capacitance and sensitivity of two photodiodes. Approximately 16 dB of DR extension was evaluated from the simulation for the situation of 10 times of sensitivity difference and the same size of parasitic capacitance between those two photodiodes.

Dynamic range expansion of active pixel sensor with output voltage feedback

In this paper, a wide dynamic range active pixel sensor(APS) with output voltage feedback structure has been designed by a 2-poly 4-metal 0.35 m standard CMOS technology. We presented a novel APS with output voltage feedback, which exhibits a wide dynamic range. The dynamic range increases at the cost of an additional diode and an additional MOSFET. The output voltage feedback structure enables the control of the output voltage level by itself, as incident light power varies. It is confirmed that the light level which the output voltage level of proposed APS is saturated is about 120,000 lux, which is higher than that of a conventional 3-transistor APS.

Resolution improvement of a CMOS vision chip for edge detection by separating photo-sensing and edge detection circuits

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with pixel array has been designed and fabricated by using 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

Analysis of the resistive network in a bio-inspired CMOS vision chip

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

A 160×120 Bio-Inspired Vision Chip for Edge Detection Using a MOS-type Photodetector for Logarithmic Active Pixel Sensor

In this paper, a vision chip for edge detection based on the structure of a biological retina is introduced. The key advantage of the structure is high speed of operation. However, the charge accumulation time of a conventional active pixel sensor limits its operation speed. In order to enhance the operation speed, a logarithmic APS using a metal-oxide-semiconductor-type photodetector was applied into the vision chip. By applying a MOS-type photodetector to a logarithmic APS, we could achieve sufficient output swing for a bio-inspired vision chip. We fabricated a 160times120 bio-inspired complementary metal-oxide-semiconductor vision chip using 0.35 mum two-poly four-metal complementary metal-oxide-semiconductor technology, and then investigated.

Bio-inspired CMOS vision chip for edge detection with electronic switches for low-power consumption

Numerical increment of analog circuits causes power consumption to increase and requires a larger chip area. In designing an analog complementary-metal-oxide-semiconductor (CMOS) vision chip for edge detection, power consumption should be considered. It restricts the number of the edge detection circuit which is based on the edge detection mechanism of vertebrate retina. In this paper, we applied electronic switches to an analog CMOS vision chip for edge detection to reduce the power consumption. Also, we propose a method to implement vision chip with higher resolution, which is to separate pixels for edge detection into a 128×128 photodetector array and a 1×128 edge detection driving circuit array. The capability to minimize power consumption was investigated by SPICE. Estimated power consumption with 128×128 pixels was below 20mW.

A bio-inspired CMOS vision chip for edge detection using an offset-free column readout circuit

The noise problem, such as the fixed pattern noise (FPN) due to the process variation, should be considered when designing a vision chip. In this paper, we proposed an edge detection circuit based on biological retina using an offset-free column readout circuit (OFCRC) to reduce the FPN occurring in the photo-detector. The OFCRC consists of one source follower, one capacitor and five transmission gates. Thus, it is simpler than a conventional correlated double sampling (CDS) circuit. A vision chip for edge detection has been designed and fabricated using a 0.35μm 2-poly 4-metal CMOS process and its output characteristics have been investigated.