Sung-Ho Suh

Vision chip for edge detection with a function of pixel FPN reduction

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

Resolution improvement of a CMOS vision chip for edge detection by separating photo-sensing and edge detection circuits

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with pixel array has been designed and fabricated by using 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

A bio-inspired CMOS vision chip for edge detection using an offset-free column readout circuit

The noise problem, such as the fixed pattern noise (FPN) due to the process variation, should be considered when designing a vision chip. In this paper, we proposed an edge detection circuit based on biological retina using an offset-free column readout circuit (OFCRC) to reduce the FPN occurring in the photo-detector. The OFCRC consists of one source follower, one capacitor and five transmission gates. Thus, it is simpler than a conventional correlated double sampling (CDS) circuit. A vision chip for edge detection has been designed and fabricated using a 0.35μm 2-poly 4-metal CMOS process and its output characteristics have been investigated.

Vision Chip for Edge and Motion Detection with a Function of Output Offset Cancellation

With a remarkable advance in CMOS (complimentary metal-oxide-semiconductor) process technology, a variety of vision sensors with signal processing circuits for complicated functions are actively being developed. Especially, as the principles of signal processing in human retina have been revealed, a series of vision chips imitating human retina have been reported. Human retina is able to detect the edge and motion of an object effectively. The edge detection among the several functions of the retina is accomplished by the cells called photoreceptor, horizontal cell and bipolar cell. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge and motion detection. The designed vision chip was fabricated using CMOS process and the characteristics were measured. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

Design of Analog CMOS Vision Chip for Edge Detection with Low Power Consumption

The problem of power consumption and the limitation of a chip area should be considered when the pixel number of the edge detection circuit increases to fabricate a vision chip for edge detection with high resolution. The numeric increment of the unit circuit causes power consumption to increase and require a larger chip area. An increment of power consumption and a limitation of chip area with several ten milli-meters square supplied by the CMOS foundry company restrict the pixel numbers of the edge detection circuit. In this paper, we proposed a electronic switch to minimize the power consumption owing to the numeric increment of the edge detection circuit to realize a vision chip for edge detection with high resolution. We also applied a method by which photodetector and edge detection circuit are separated to implement a vision chip with a higher resolution. The photodetector circuit with pixels uses a common edge detection circuit with pixels so that resolution was improved at the same chip area. The chip size is and the power consumption was confirmed to be about 20mW using SPICE.