Jaeduk Han

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.

A 60Gb/s 173mW receiver frontend in 65nm CMOS technology

This paper presents a 65nm CMOS 60Gb/s receiver frontend incorporating CTLE, FFE, DFE, output slicers and clock generation as well as distribution circuits. Current-integration along with cascode gain control is used to maintain equalizer linearity under varying gain without sacrificing power consumption. Interleaved deserializing slicers achieve the high gain required for adaptive error sampling. The receiver operates error free over >1e12 bits at 60Gb/s, occupies 0.16mm2, and consumes 173mW.

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET

The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S21 of a channel resembling such interconnects and the corresponding single-pulse response after TX-FIR and RX CTLE. Although the S21 is merely ∼10dB at 14GHz, the single-pulse response exhibits significant reflections from impedance discontinuities, mainly between package and PCB traces. These reflections are detrimental to PAM-4 signaling and cannot be equalized effectively by RX CTLE and/or a few taps of TX feed-forward equalization. This paper presents the design of a PAM-4 receiver using 10-tap direct decision-feedback equalization (DFE) targeting such VSR channels.

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28–40nm CMOS processes have been demonstrated for <20dB loss channels with energy efficiencies ranging from 4.4 to 11.96pJ/b. In order to support channels with higher losses, the half-rate 65nm receiver front-end design described in [3] includes a 3-tap DFE, a 2-tap FFE, and a CTLE at ∼2.88pJ/b, but neither closed-loop equalizer adaptation nor clock and data recovery were demonstrated. Closing these loops is especially critical in such an interleaved architecture, since at these data-rates each interleaved datapath can result in a noticeably different overall channel response (ISI), and the need for closed-loop CDR is self-evident. This paper therefore presents a fully adaptive 60Gb/s transceiver, supporting >20dB channel loss, implemented in a 65nm CMOS technology (Fig. 6.2.1). The full transceiver (including baud-rate CDR) achieves 60Gb/s and 4.8pJ/b energy efficiency over a 0.7m Twinax cable.

A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications

Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-limited channels. We implemented a 3-tap DFE receiver for 5-Gb/s data bandwidth. To realize a multi-tap DFE operation, a digital-control scheme is proposed that does not use analog circuits for biasing, such as DACs. In addition to the conventional loop unrolling, several techniques including combined feedback are used to reduce the latency of the feedback path. Fabricated in a 0.13-μm CMOS process, the prototype of the proposed DFE core has an area of 0.009 mm2 and consumes 8.4 mW from a 1.2-V supply, achieving a BER of less than 10−11 over a pair of 28-inch Nelco 4000–6 board traces.