Jaehyun Yang

High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals

Unlike graphene, the existence of bandgaps (1-2 eV) in the layered semiconductor molybdenum disulphide, combined with mobility enhancement by dielectric engineering, offers an attractive possibility of using single-layer molybdenum disulphide field-effect transistors in low-power switching devices. However, the complicated process of fabricating single-layer molybdenum disulphide with an additional high-k dielectric layer may significantly limit its compatibility with commercial fabrication. Here we show the first comprehensive investigation of process-friendly multilayer molybdenum disulphide field-effect transistors to demonstrate a compelling case for their applications in thin-film transistors. Our multilayer molybdenum disulphide field-effect transistors exhibited high mobilities (>100 cm(2) V(-1) s(-1)), near-ideal subthreshold swings (~70 mV per decade) and robust current saturation over a large voltage window. With simulations based on Shockleys long-channel transistor model and calculations of scattering mechanisms, these results provide potentially important implications in the fabrication of high-resolution large-area displays and further scientific investigation of various physical properties expected in other layered semiconductors.

Improved Growth Behavior of Atomic-Layer-Deposited High-k Dielectrics on Multilayer MoS2 by Oxygen Plasma Pretreatment

We report on the effect of oxygen plasma treatment of two-dimensional multilayer MoS2 crystals on the subsequent growth of Al2O3 and HfO2 films, which were formed by atomic layer deposition (ALD) using trimethylaluminum and tetrakis-(ethylmethylamino)hafnium metal precursors, respectively, with water oxidant. Due to the formation of an ultrathin Mo-oxide layer on the MoS2 surface, the surface coverage of Al2O3 and HfO2 films was significantly improved compared to those on pristine MoS2, even at a high ALD temperature. These results indicate that the surface modification of MoS2 by oxygen plasma treatment can have a major impact on the subsequent deposition of high-k thin films, with important implications on their integration in thin film transistors.

The effect of ZnO surface conditions on the electronic structure of the ZnO/CuPc interface

The interfacial electronic structures of zinc oxide (ZnO)/copper-phthalocyanine (CuPc) were investigated by in situ x-ray and ultraviolet photoelectron spectroscopy (UPS) to determine the effects of air contamination on the ZnO substrate. UPS spectra showed that the 0.2 eV of the interface dipole is generated at the interface of the air exposed ZnO/CuPc while the interface of the annealed ZnO/CuPc generated −0.2 eV. In both cases, no band bending was observed. On the other hand, band bending at 0.3 eV and an interface dipole of 0.2 eV were observed at the interface of the sputter cleaned ZnO/CuPc. The energy offset between the conduction band maximum of ZnO and the highest occupied molecular orbital of CuPc was determined to be 0.6–0.7 eV for the contaminated ZnO interface while the offset was 1.0 eV for the cleaned ZnO interface. Contaminating moisture has little effect on the offset while the charge transfer was blocked and the offset was decreased in the presence of hydrocarbons.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

MoS2–InGaZnO Heterojunction Phototransistors with Broad Spectral Responsivity

We introduce an amorphous indium-gallium-zinc-oxide (a-IGZO) heterostructure phototransistor consisting of solution-based synthetic molybdenum disulfide (few-layered MoS2, with a band gap of ∼1.7 eV) and sputter-deposited a-IGZO (with a band gap of ∼3.0 eV) films as a novel sensing element with a broad spectral responsivity. The MoS2 and a-IGZO films serve as a visible light-absorbing layer and a high mobility channel layer, respectively. Spectroscopic measurements reveal that appropriate band alignment at the heterojunction provides effective transfer of the visible light-induced electrons generated in the few-layered MoS2 film to the underlying a-IGZO channel layer with a high carrier mobility. The photoresponse characteristics of the a-IGZO transistor are extended to cover most of the visible range by forming a heterojunction phototransistor that harnesses a visible light responding MoS2 film with a small band gap prepared through a large-area synthetic route. The MoS2-IGZO heterojunction phototransistors exhibit a photoresponsivity of approximately 1.7 A/W at a wavelength of 520 nm (an optical power of 1 μW) with excellent time-dependent photoresponse dynamics.

Bias-stability improvement using Al2O3?interfacial dielectrics in a-InSnZnO thin-film transistors

We report amorphous-indium–tin–zinc-oxide (a-ITZO) thin-film transistors (TFTs) obtained using an aluminum-oxide (Al2O3) interfacial dielectric using atomic layer deposition between a silicon-nitride (SiNX) gate dielectric and an a-ITZO active channel layer. The effect of the Al2O3 interfacial layer on the suppression of charge trapping in a-ITZO TFTs is presented. In transparent oxide TFTs, reducing the shift in threshold voltage by stress-including negative-bias stress (NBS) is one of the key issues in improving the stability performance of TFTs. The NBS stability of an a-ITZO TFT using an Al2O3/SiNX double-layered dielectric is superior to that using an SiNX single-gate dielectric, because of the smooth surface with a root-mean-square roughness of 0.147 nm and a low defect density of less than 3×1011 eV−1 cm−2, which increases hydrophobicity. The a-ITZO TFTs using the Al2O3 interfacial dielectric show little change in the threshold voltage (~0 V), and a long trapping time of ~5000 s when a gate voltage of −25 V and drain voltage of 1 V are applied for 10 000 s. We show that the gate dielectric has a profound effect on the electrical stability, and suggest a way of improving the stability of a-ITZO TFTs.

Hybrid ZnO nanowire networked field-effect transistor with solution-processed InGaZnO film

We examined the effect on the transistor properties of the spatial gaps between nanowires that may randomly exist in the nanonet-structured, ZnO transistor. A hybrid-type, ZnO nanowire-based transistor was fabricated by combining the nanonet-structured ZnO nanowire arrays with a solution-deposited InGaZnO (IGZO) film and its performance was compared with that of the device without the IGZO film. By filling the disconnected carrier paths (gaps) between the arrayed ZnO nanowires with IGZO solution coating, much improved transistor characteristics, such as a narrow threshold voltage distribution and minimized multiple turn-on behavior, were obtained, which highlighted the importance of the gap filling in the nanonet transistors.

A Triple-Layered Microcavity Structure for Electrophoretic Image Display

An electrophoretic display (EPD) cell with a triple-layered microcavity structure was fabricated using a convenient dry film resist. The inherent structural advantage arising from the function of the middle channel layer as a background colored state enabled the EPD to operate with two different-colored states by using a single type of electronic-ink particles, thereby eliminating the possible agglomeration of oppositely charged ink particles and supporting the potential application of the proposed structure to color the electronic paper. The preliminary operation of this new EPD structure was demonstrated as white and blue display states on a rigid glass exhibiting a contrast ratio of 1.5 : 1 with saturation voltages of + 30 and -30 V, respectively. Successful demonstrations on both the indium-tin-oxide-patterned glass and flexible polyethylene substrates are also provided.