Jaemyoung Lee

Optical clock recovery scheme for a high bit rate nonreturn-to-zero signal using fiber Bragg grating filters

For optical clock recovery of nonreturn-to-zero (NRZ) signals more than 40 Gb/s, we propose and experimentally demonstrate a simple clock recovery scheme using beat processing. Through the proposed scheme, we square the adjustment range of the variable optical attenuator (VOA) and achieved an enhanced clock-to-noise ratio (CNR) of more than 15 dB in the experiment, compared to a system without the proposed scheme.

Shockwave Velocity Estimation from Laser Induced Breakdown Images

Laser-induce breakdown at early time is analyzed in terms of the shockwave velocity using an Nd:YAG laser. The shockwave velocities are estimated by capturing the shockwave propagation images of a 20 μm glass microsphere through the Schlieren method. The velocity estimation from images shows that the forward shockwave is faster than the backward. The forward and backward velocities within 30 ns from the breakdown are approximately 5.5 Km/s and 3.5 Km/s, respectively.

Laser-induced breakdown mechanisms of a glass microsphere

Laser energy distributions of 20 μm and 40 μm glass microspheres were calculated with different laser wavelengths. Most simulation results show similar energy distributions in which laser energies are focused at the backside of the microsphere. Using time-resolved optical shadow images and Schlieren images, initial breakdown location and shockwave propagation from the breakdown were investigated for 20 μm glass microsphere which was ablated by Nd:YAG laser with a wavelength of 1.064 μm. Time-resolved imaging showed the location of the initial breakdown and the shockwave motion over its first 300 μm of expansion. Measured shockwave velocities were in the range of 1-10 km/s and showed a linear dependence on laser fluence within 30 ns.

Optical PRZ signals of an optical clock generation scheme using an FBG filter

We propose an optical clock generation scheme and investigate characteristics of generated clock signals through a fiber Bragg grating (FBG) filter. The equation for the clock component in an optical spectrum indicates that disturbance of the optical spectrum of a nonreturn-to-zero (NRZ) signal can generate NRZ clock signal. Optical experiment of the clock generation scheme for a 10 Gb/s NRZ signal shows the pseudoreturn-to-zero (PRZ) signals through the scheme.

Enhanced working distance of fiber lens with low refractive index material

We proposed a new structure for fiber lens to extend the working distance by applying polymer layer to the fiber lens. The simulation result shows that the working distance can be extended to larger than 10 times than a fiber lens without a coated layer. In simulation, the proposed structure extended the working distance to about 2,110 μm by using polymer layer with a refractive index of 1.3.

Optical Clock Signal Extraction of Nonreturn-to-Zero Signal by Suppressing the Carrier Component

We propose a simple optical clock signal extraction scheme of a nonreturn-to-zero signal and experimentally demonstrate the clock signal extraction using a single FBG filter. The proposed optical signal processing shows the 10Gb/s PRZ pattern which can be used for optical clock recovery.

Physical modeling of laser-induced breakdown of glass

We made a physical model for investigation of laser-induced breakdown of glass. To estimate the laser energy absorption through electron heating, we derive a power transfer rate equation and an electron number density equation for a steady state as a function of temperature and electric field. Numerical simulations using the derived equations show that the laser power absorption dependence of glass on temperature and electric field strength.

Design and verification for hierarchical power efficiency system (HPES) design techniques using low power CMOS digital logic

This paper presents the design implementation of digital circuit and verification method for power efficiency systems, focused on static power consumption while the CMOS logic is in standby mode. As complexity rises, it is necessary to study the effects of system energy at the circuit level and to develop accurate fault models to ensure system dependability. Our approach to designing reliable hardware involves techniques for hierarchical power efficiency system (HPES) design and a judicious mixture of verification method is verified by this formal refinement. This design methodology is validated by the low power adder with functional verification at the chip level after satisfying the design specification. It also describes a new HPES integration method combining low power circuit for special purpose computers. The use of new circuits and their corresponding HPES design techniques leads to minimal system failure in terms of reliability, speed, low power and design complexity over a wide range of integrated circuit (IC) designs.