Hyunwoo Cho

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

Finite state machine (FSM) verification based on implicit state enumeration can be extended to test generation and redundancy identification. The extended method constructs the product machine of two FSMs to be compared, and reachability analysis is performed by traversing the product machine to find any difference in I/O behavior. When an output difference is detected, the information obtained by reachability analysis is used to generate a test sequence. This method is complete, and it generates one of the shortest possible test sequences for a given fault. However, applying this method indiscriminately for all faults may result in unnecessary waste of computer resources. An efficient method based on reachability analysis of the fault-free machine (three-phase ATPG) in addition to the powerful but more resource-demanding product machine traversal is presented. The application of these algorithms to the problems of generating test sequences, identifying redundancies, and removing redundancies is reported. >

ATPG aspects of FSM verification

Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states.<<ETX>>

Algorithms for Approximate FSM Traversal

In this paper we present algorithms for approximate FSM traversal based on state space decomposition. The original FSM is partitioned in sub-machines, and each of them is traversed separately; the result is an over-estimation of the set of reachable states. Several traversal strategies are discussed. Good partitioning is important for the performance of the traversal techniques; a method to heuristically find an appropriate decomposition, based on the exploration of the FSM latch connection graph, is proposed. Applications of the approximate traversal methods to sequential optimization and behavioral verification of FSMs are described; experimental results for such applications, together with data concerning pure traversal, are reported.

Synchronizing sequences and symbolic traversal techniques in test generation

Asynchronizing sequence drives a circuit from an arbitrary power-up state into a unique state. Test generation on a circuit without a reset state can be much simplified if the circuit has a synchronizing sequence. In this article, a framework and algorithms for test generation based on themultiple observation time strategy are developed by taking advantage of synchronizing sequences. Though it has been shown that the multiple observation time strategy can provide a higher fault coverage than the conventional single observation time strategy, until now the multiple observation time strategy has required a very complex tester operation model (referred asMultiple Observation time-Multiple Reference strategy (MOMR) in the sequel) over the conventional tester operation model. The overhead of MOMR, exponential in the worst case, has prevented widespread use of the method. However, when a circuit is synchronizable, test generation can employ the multiple observation time strategy and provide better fault coverages, without resorting to MOMR. This testing strategy is referred asMultiple Observation time-Single Reference strategy (MOSR). We prove in this article that the same fault coverage, that could be achieved in MOMR, can be obtained in MOSR, if the circuit under test generation is synchronizable. We investigate how a synchronizing sequences simplifies test generation and allows to use MOSR under multiple observation time strategy. The experimental results show that higher fault coverages and large savings in CPU time can be achieved by the proposed framework and algorithms over both existing single observation time strategy methods as well as other multiple observation time strategy methods.

Algorithms for approximate FSM traversal based on state space decomposition

This paper presents algorithms for approximate finite state machine traversal based on state space decomposition. The original finite state machine is partitioned in component submachines, and each of them is traversed separately; the result of the computation is an over-estimation of the set of reachable states of the original machine. Different traversal strategies, which reduce the effects of the degrees of freedom introduced by the decomposition, are discussed. Efficient partitioning is a key point for the performance of the traversal techniques; a method to heuristically find a good decomposition of the overall finite state machine, based on the exploration of its state variable dependency graph, is proposed. Applications of the approximate traversal methods to logic optimization of sequential circuits and behavioral verification of finite state machines are described; experimental results for such applications, together with data concerning pure traversal, are reported.

Fast sequential ATPG based on implicit state enumeration

The knowledge of the State Transition Graph (STG) of a sequential circuit helps in generating test sequences. For instance, by determining that a set of states is not reachable from the reset state, it is possible to identify a certain type of sequentially untestable faults. However, until recently, the ability of algorithms to store the STG of a sequential circuit has been limited to small instances. Recent advances in sequential circuit verification, based on the use of binary decision diagrams and new powerful implicit enumeration algorithms, have dramatically improved our ability to deal with large numbers of states. In this paper we report on the application of these algorithms to the problems of generating justification sequences, identifying redundancies, and dealing with hard-to-detect faults. Our experiments show substantial improvements over previously published results.

Timing analysis of combinational circuits using ADDs

This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADDs). The procedure we propose, implemented as on extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gate-level representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst-case primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for low-power consumption.<<ETX>>

Redundancy identification and removal based on implicit state enumeration

The knowledge of the state transition graph (STG) of a sequential circuit helps in generating test sequences and identifying redundancies. The application of algorithms to the identification and removal of redundancies is reported. This strategy is based on traversing the STG of the given circuit and then performing redundancy identification using the reachability information calculated by the traversal. This method considers one candidate redundancy at a time, in an order that tries to minimize the total processing time. Substantial area and delay reductions are achieved. Experiments show that for many circuits 100% of the sequentially redundant faults can be eliminated in very reasonable amounts of time.<<ETX>>

New ATPG techniques for logic optimization

Algorithms are presented for RI (redundancy identification) and RR (redundancy removal). With fault simulation and a backtrack limit of 10, the RI program is able to find a test for all testable faults and identify all the redundant faults in each of the ISCAS benchmark examples. The RR program makes the whole benchmark set 100% testable for single stuck-at faults, and generates the test, in less than 1 CPU hour (SUN4/280). The algorithms were developed for equivalence-based logic optimization applications, which accentuate the role of heuristics in the process of automatic test program generation (ATPG), since this diminishes the role of fault simulation. The authors compare a limited set of results obtained by RR to those of existing logic optimization programs. The results show that in most cases, superior results can be obtained with factors of tens to hundreds speedup in CPU time.<<ETX>>

BEATNP: a tool for partitioning Boolean networks

BEATNP (BoolEAn Tools Network Partitioner) was designed to extend the application size capability of the BOLD (Boulder Optimal Logic Design) system. BEATNP partitions a Boolean network into subnetworks which satisfy user specified size constraints. Most of the tools in the BOLD tools suite solve problems which are in NP or Co-NP, so they can be assumed to have exponential complexity. Because the BEATNP algorithms have log-linear worst-case complexity, the CPU time requirements of optimization tools can be reduced greatly in difficult cases. When used with the BOLD minimizer on a set of well known benchmark examples, BEATNP reduced CPU time by 1 to 3 orders of magnitude while retaining a significant majority of the optimization savings available in the unpartitioned case.<<ETX>>