Jakob Kriz

Investigation of barrier formation and stability of self-forming barriers with CuMn, CuTi and CuZr alloys

In this work, we present the recent work on self-forming barriers. Focus on investigation laid on the barrier formation and its stability against copper diffusion. The investigated alloys were Cu(Mn), Cu(Ti) and Cu(Zr) respectively. It can be shown that these alloys are capable to form an enrichment layer on the SiO2 interface. Here the substrate influences mainly the thickness of the generated barrier. Electrical measurements show the barrier stability against copper diffusion. Mn and Ti are promising elements as barrier materials.

Cu barrier properties of very thin Ta and TaN films

As a result of the continuous miniaturization of integrated circuits, width and depth of Cu interconnects are reduced for every new technology node, implying that also the Ta or TaN Cu diffusion barrier and Cu seed layer must be thinned in order to avoid top feature pinch-off during Cu electroplating [1]. On the other hand, a reduction of Ta or TaN film thickness may also be desirable from a cost perspective, e.g. in ICs with less aggressive scaling. Cabral et al. showed that a 1 nm TaN film prevented Cu diffusion upon annealing at temperatures below 650 °C [2]. However, no electric fields were applied in this study, and TaN was deposited on Si. This paper reports on the Cu barrier performance of very thin Ta and TaN films (1 to 3nm) deposited by PVD DC magnetron sputtering on different types of dielectrics. Ta and TaN thicknesses were verified by transmission electron microscopy (TEM). Metal-insulator-semiconductor (MIS) film stacks were applied as test structures ( see fig. 1), and thermal and PECVD SiOz were utilized as isolators. As confirmed by FTIR measurements, they significantly differ in the availability of weakly bonded oxygen, present in form of silanol groups (see fig. 2). The barrier evaluation itself consisted of a combination of an initial thermal anneal, electrical bias temperature stress (BTS) and triangular voltage sweep (TVS) measurements. The test structure preparation and the triangular voltage sweep (TVS) measurement procedure applied in this study were described in detail previously [ 3, 4].High temperature annealing between 350°C and 600°C shall simulate a thermal budget during manufacturing, including a reliability buffer. BTS is applied because both electrical fields and Joule heating are present in Cu interconnects during chip operation, and both are driving forces for a mobility of Cu atoms. Triangular voltage sweep (TVS) measurements are applied for Cu detection since they are directly related to a movement of Cu ions, and the sensitivity ofTVS (1E + 10 Cu ions/cm2) is up to three orders of magnitude higher compared to analytical techniques like SIMS (1E+13-1E+14 Cu ions/cm2).

Qualification of extrinsics in BEOL - the new challenge

Extrinsic failure behavior of vias and dielectrics in the backend of line (BEOL) has been studied using dedicated test structures on a large scale. Via fails after (unbiased) stress were detected utilizing a test set-up and program that allows the readout of more than 109 individual vias per wafer. The isolation behavior of intra and inter level BEOL dielectrics was studied by performing breakdown tests on various types of complex via/metal line structures covering layout areas above 1cm2 per wafer. Extrinsic failures of vias and dielectrics were linked to process or design marginalities. The study of both, resistance and isolation related defects allows a comprehensive assessment of the electrical defect density (eDD) in the BEOL to enable process and design improvements to ensure a “zero defect” product roadmap.