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Dive into the research topics where Jama I. Barreh is active.

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Featured researches published by Jama I. Barreh.


international symposium on microarchitecture | 2012

Sparc T4: A Dynamically Threaded Server-on-a-Chip

Manish Shah; Robert T. Golla; Greg Grohoski; Paul J. Jordan; Jama I. Barreh; Jeffrey S. Brooks; Mark Greenberg; Gideon N. Levinsky; Christopher H. Olson; Zeid Hartuon Samoail; Matt Smittle; Thomas A. Ziaja

The Sparc T4 is the next generation of Oracles multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4s key features and detail the microarchitecture of the dynamically threaded S3 processor core, which is implemented on Sparc T4.


Archive | 2009

PHYSICALLY-INDEXED LOGICAL MAP TABLE

Robert T. Golla; Jama I. Barreh; Howard L. Levy


Archive | 2009

PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITIONAL BRANCH INSTRUCTIONS ON A MULTITHREADED PROCESSOR

Manish Shah; Gregory F. Grohoski; Robert T. Golla; Jama I. Barreh


Archive | 2009

LOGICAL MAP TABLE FOR DETECTING DEPENDENCY CONDITIONS

Robert T. Golla; Jama I. Barreh; Jeffrey S. Brooks; Howard L. Levy


Archive | 2004

Arbitrating cache misses in a multithreaded/multi-core processor

Jama I. Barreh; Manish Shah


Archive | 2009

DYNAMIC TAG ALLOCATION IN A MULTITHREADED OUT-OF-ORDER PROCESSOR

Paul J. Jordan; Robert T. Golla; Jama I. Barreh


Archive | 2004

Delay slot handling in a processor

Robert T. Golla; Paul J. Jordan; Jama I. Barreh


Archive | 2009

Logical map table for detecting dependency conditions between instructions having varying width operand values

Robert T. Golla; Jama I. Barreh; Jeffrey S. Brooks; Howard L. Levy


Archive | 2009

Processor operating mode for mitigating dependency conditions

Robert T. Golla; Paul J. Jordan; Jama I. Barreh; Matthew B. Smittel; Yuan C. Chou; Jared C. Smolens


Archive | 2004

Hybrid instruction buffer

Robert T. Golla; Yue Chang; Jama I. Barreh

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