James A. Barby

Polynomial splines for MOSFET model approximation

The approximation of MOSFET nonlinearities by use of polynomial splines was investigated for reducing both circuit model development time and model simulation cost. After a brief tutorial on spline functions, it is shown how the number of independent variables for the MOSFET simulation models in digital circuits is reduced by their use. A tableau formulation for generating splines is presented along with a storage-reduction technique for polynomial spline coefficients. Mathematical programming problems for one-, two-, and three-dimensional splines are given that result in accurate monotonic splines using few segments. Two spline segments are shown to provide sufficient accuracy in the one-dimensional case, while 4*4 and 2*5*5 segments provide sufficient accuracy in the two- and three-dimensional cases, respectively. >

Group delay as an estimate of delay in logic

A method is presented for fast calculation of interconnect delay in bipolar of MOS logic networks. It has been established experimentally on many RC lumped networks with arbitrary topologies that the usually defined delay (mid-point for a unit step input), and the group delay at zero frequency, are related by a proportionality constant. Also it has been found that the property remains valid for arbitrarily positioned taps along the network. Derivations give formulas for an efficient numerical method to calculate the group delay and its derivatives with respect to network elements. In connection with mathematical optimization, the method can be used to design taps or branches with prescribed delays. >

Current-limited switch-level timing simulator for MOS logic networks

An algorithm for switch-level timing simulation of MOS logic networks is proposed. The event-driven simulator, WATSWITCH, partitions the circuit into subblocks which are solved by replacing each transistor by a special current-limited switch. Because of the choice of the switch model, time-domain responses are obtained without model evaluations during the simulation, without table lookup, and without time-domain integration. This is achieved by allowing only capacitors and piecewise-constant current sources to be the elements of the simulator. Because resistors are not allowed, the time responses are known to be piecewise-linear segments. As a consequence, neither numerical integration nor transistor model evaluation is needed during the simulation. >

Analog functional simulator for multilevel systems

The authors describe a high-level functional analog simulator for hybrid logic/analog networks. it forms one level of an experimental multilevel simulation system which is currently under development. The functional simulator is described in detail, and the structure of the multilevel simulator is briefly outlined. It can be used as a stand-alone system but was developed specifically for coupling with other levels of simulation which also use time responses (or voltage waveforms). Since Boolean algebra cannot operate with time responses, a new algebra is developed. It eliminates the unknown state, the main obstacle in coupling analog simulation to logic simulation. Logic states are replaced by operations on time functions, in this case represented by piecewise linear segments. High-level analog operations are also possible. The simulator based on these ideas was used to solve several high-level analog problems. The examples presented demonstrate its application. >

Logic simulation with current-limited switches

A switch-level logic simulator for MOS networks based on the theory of current-limited switches is described. It was derived from a switch-level timing simulator by suppressing time-related information and by eliminating invalid events. The simulator obeys Kirchoffs laws and after initialization every node has a known voltage. It can thus be used to drive analog simulation. Fault simulation is easily incorporated by representing the line-open fault by an open circuit and the node-short fault by a short circuit. Examples demonstrate application to both logic and fault simulation. >

CircuitSim93: A circuit simulator benchmarking methodology case study

A circuit simulator benchmarking methodology is developed that follows the philosophy that one wants to exercise each of the simulators on each of the benchmark circuits and make a fair comparison of their performance. This methodology was tested out in a benchmarking of six commercial circuit simulators from three CAE companies using a new circuit simulator benchmark suite called CircuitSim93.<<ETX>>

A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit

A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.

An architecture for integrated reliability simulators using analog hardware description languages

A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented.

Creative Methods of Leveraging VHDL-AMS-like Analog-HDL Environments. Case Study: Simulation of Circuit Reliability

Given an Analog Hardware Description Language (Analog-HDL), like the proposed VHDL-AMS, one can do much more than conventional component modeling. One can develop additional simulation capabilities by creatively using the Analog-HDL/VHDL-AMS environment. To demonstrate this, we present an innovative method of implementing simulation of systems whose equations (or parameters) change with time (such as reliability simulation, component failure modeling and sensitivity analysis). The simulation algorithm is defined in terms of event-driven control modules, signals and interfaces within a generic Analog-HDL environment. To verify our methodology, we use this configuration to implement three different circuit reliability simulation algorithms. We describe the different modules required to implement the algorithm in terms of IEEE 1076.1 PseudoCode routines. Our implementation allows the definition of two concurrent versions of time within the same simulation. We present a comparison of the results obtained from applying the three reliability simulation algorithms to amorphous silicon thin-film transistor circuits.

Switched-current filter models for frequency analysis in the continuous-time domain

A simulation and modeling methodology for switched-current (SI) filters is described, and some results are presented. These results, which differ from the response that a true sampled-data filter would predict from z-plane analysis, demonstrate the need to investigate the complete response of an SI filter to a continuous-time input waveform. It is shown that current mirrors with a large g/sub m/:g/sub o/ ratio are required for SI filters, and that the stopband response of many SI filters is strongly dependent on the sampling time of the input sample-and-hold circuit.<<ETX>>