Kishore Singhal

Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies

Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.

A New Simulation Method for NBTI Analysis in SPICE Environment

This paper presents a simulation framework for reliability analysis of circuits in the SPICE environment. The framework incorporates the degradation of physical parameters such as threshold voltage (Vtp) into circuit simulation and enables the design of highly reliable circuits. The parameter degradation is based on the numerical solution for the reaction-diffusion (R-D) mechanism, which is a general model applicable to various reliability effects such as NBTI, HCI, NCS, and SEE. In particular, the accuracy and efficiency of this method was verified for NBTI degradation with 130nm experimental and simulation data over a wide range of stress voltages and temperature. The model also accurately captures the dependence of NBTI on multiple diffusion species (H/H2), key process (Vth, tox) and environmental parameters (VDD, temperature). The circuit level performance of this method is verified with silicon data from ring-oscillator circuit. We also investigated the predicted impact of NBTI on representative digital circuits

Fast and memory-efficient minimum spanning tree on the GPU

The GPU is an efficient accelerator for regular data-parallel workloads, but GPU acceleration is more difficult for graph algorithms and other applications with irregular memory access patterns and large memory footprints. The minimum spanning tree MST problem arises in a variety of applications and its solution exemplifies the difficulties of mapping irregular algorithms to the GPU. In this paper, we present a memory-efficient parallel algorithm for finding the minimum spanning tree of very large graphs by introducing a data-parallel implementation of Kruskals algorithm. We test scalability and performance on random and real-world graphs with up to 25 million vertices and 240 million edges on an Nvidia Tesla T10 GPU with 4GB of memory. Our method can process graphs 4X larger and up to 10X faster than was possible with the recently published implementation of Boruvkas MST algorithm for the GPU. We also demonstrate the performance advantage of the proposed method against the multi-core filter-Kruskals MST algorithm on a dual quad-core CPU server with Nehalem X5550 processors.

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized

Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations

On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (/spl sim/9% push-out vs. RC delay) and noise (/spl sim/2/spl times/ RC noise). Device and interconnect variations add /spl sim/4% into RLC max-timing impact, while their impact on RLC signal noise is nonappreciable.

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (~ 10% pushout versus RC delay) and noise (~2timesRC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add ~ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales

Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond

The on-chip inductance impact on signal integrity has been a problem for designs in deep-submicron technologies. The impact increases clock skew, max-timing and noise levels of bus signals. In this paper, circuit macro-models are bench-marked against test chip measurement in a 90 nm technology. Circuit simulations show the inductive impact on clock skew (e.g., 1lps in 2GHz clock frequency), signal delay (e.g., 11% max-timing push-out) and noise levels (e.g., 13% VDD). In addition, the inductive impact on signal integrity in the presence of process variations is evaluated. Finally, inductive impact in 65nm and 45 nm technologies is simulated, which indicates that the inductance impact will not diminish as technology scales.