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Dive into the research topics where James Arthur Farrell is active.

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Featured researches published by James Arthur Farrell.


IEEE Journal of Solid-state Circuits | 1998

Issue logic for a 600-MHz out-of-order execution microprocessor

James Arthur Farrell; Timothy Charles Fischer

The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.


Archive | 1998

Speculative issue of instructions under a load miss shadow

Daniel L. Leibholz; Sven Eric Meier; James Arthur Farrell; Timothy Charles Fischer; Derrick R. Meyer


Archive | 2002

METHOD FOR MAPPING INSTRUCTIONS USING A SET OF VALID AND INVALID LOGICAL TO PHYSICAL REGISTER ASSIGNMENTS INDICATED BY BITS OF A VALID VECTOR TOGETHER WITH A LOGICAL REGISTER LIST

James Arthur Farrell; Sharon M. Britton; Harry R. Fair; Bruce Gieseke; Daniel L. Leibholz; Derrick R. Meyer


Archive | 1998

Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency

James Arthur Farrell; Bruce Gieseke


Archive | 2003

Method and circuits for early detection of a full queue

Timothy Charles Fischer; Daniel L. Leibholz; James Arthur Farrell


Archive | 1998

Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle

James Arthur Farrell; Bruce Gieseke


Archive | 1999

Method for compacting an instruction queue

James Arthur Farrell; Timothy C. Fischer; Daniel Lawrence Leibholz; Bruce Gieseke


Archive | 1998

Technique for ordering internal processor register accesses

Daniel L. Leibholz; Sharon Marie Britton; James Arthur Farrell; Timothy Charles Fischer


Archive | 1999

Method and apparatus for performing timing verification of a circuit

Nevine Nassif; James Arthur Farrell; Dale Hayward Hall; Gill Watt


Archive | 2002

Timing verifier for MOS devices and related method

Nevine Nassif; Madhav Desai; James Arthur Farrell; Harry Ray Fair; Roy Badeau; Nicholas L. Rethman

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