Timothy Charles Fischer

Issue logic for a 600-MHz out-of-order execution microprocessor

The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU

AMDs 2-core “Bulldozer” module contains 213 million transistors in an 11-metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture [1] improves performance and frequency while reducing area and power compared to a previous AMD x86–64 CPU in the same process [2]. To achieve these goals, the design reduced the number of FO4 inverter delays/cycle by more than 20%, achieving higher frequencies in the same power envelope even with increased core counts. The 2-core CPU module area (including 2MB L2 cache) is 30.9mm2 (Fig. 4.5.7).

Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS

This paper describes key circuit innovations in a new x86-64 micro-architecture AMD code-named “Bulldozer” , . It is implemented in 32 nm high-K metal gate SOI CMOS. It occupies 30.9 mm-2, contains 213 million transistors, reduces the number of F04 gates per cycle by more than 20% compared to a previous processor in the same technology , and demonstrates superior frequency scaling across voltage. The module includes two independent integer cores but shares the fetch, decode, floating-point, and L2 cache units to maximize single-threaded performance and multi-threaded throughput while significantly improving power and area efficiency compared to fully replicated CPU cores. The design includes a new soft-edged flop (SEF) family to enable high frequency and low power. Achieving power efficiency in combination with high-frequency design is a particular challenge, and this paper describes several of the unique approaches to power optimization that have been employed in the design. The gate-count reduction and power optimization enable faster frequencies in the same power envelope compared to previous designs.

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

This special issue of the IEEE Journal of Solid-State Circuits is dedicated to the papers taken from the best of the Data Converters, RF, Analog,Wireless Communications, andWireline Communications sessions at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, CA, USA in February 2012. The guest editors of this special issue would like to thank all the presenters at the conference from these sessions for making the selection process quite difficult, as the overall standard was quite high. We would also like to extend our appreciation to the selected authors for their timely and excellent submissions, and to those reviewers who helped ensure the papers met our high quality level. Seven papers have been selected from the data converter sessions in the 2012 ISSCC for inclusion in this special issue. Seven papers have been selected from the three RF sessions at the ISSCC 2012, ranging from radio receivers to power amplifiers, PLL andmodulators, and THz imagers and power sources. The six papers in the Analog Techniques Section tackle highpower to high-speed applications that span technology nodes from 0.8μm down to 65 nm, utilizing BCD, BiCMOS, and CMOS processes in various designs. Six papers have been carefully selected from three Wireless sessions at ISSCC 2012. These papers cover a wide range of topics which represent diversified applications in wireless communications. Finally, five papers have been selected from three Wireline sessions at ISSCC 2012.