James B. Kuo

Low-voltage SOI CMOS VLSI devices and circuits

Preface. Acknowlegments. Introduction. SOI CMOS Devices--Part I. SOI CMOS Devices--Part II. Fundamentals of SOI CMOS Circuits. SOI CMOS Digital Circuits. SOI CMOS Analog Circuits. PD SOI-Technology SPICE Models. Index.

Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices.

An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating

This paper reports a closed-form analytical drain current model considering both electron and lattice temperatures simultaneously using a quasi-two-dimensional approach for deep submicron ultrathin SOI NMOS devices. As verified by the experimental data, the closed-form analytical model shows a good predication of the negative differential resistance behavior. Based on the analytical model, with a channel length of >

Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure

This paper presents analysis of the fringing electric field effect on the threshold voltage of fully depleted (FD) silicon-on-insulator nMOS devices with the lightly doped drain (LDD)/sidewall oxide spacer structure based on a closed-form analytical model derived from the two-dimensional (2-D) Poissons equation and using the conformal mapping technique. Based on the analytical model, as verified by the experimental data and the 2-D simulation results, with a lower n-LDD doping density, the fringing electric field effect in the sidewall oxide spacer lowers the short-channel effect.

An analytical back-gate bias effect model for ultrathin SOI CMOS devices

An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed. >

A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-/spl mu/m CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained.

Temperature-dependent kink effect model for partially-depleted SOI NMOS devices

This paper reports a closed-form analytical temperature-dependent kink effect model for the partially-depleted SOI NMOS devices. Based on the body-emitter voltage model, an analytical triggering V/sub DS/ formula for temperature-dependent kink effect has been obtained. According to the analytical model, at a higher operation temperature and with a lighter thin-film doping density, the onset of the kink effect occurs at a larger V/sub DS/.

An analytical a-Si:H TFT DC/capacitance model using an effective temperature approach for deriving a switching time model for an inverter circuit considering deep and tail states

This paper presents an analytical a-Si:H DC/capacitance model using an effective temperature approach for deriving a switching time model for an inverter circuit considering deep and tail states. Using an effective temperature approach, the localized deep and tail states have been considered in the DC/capacitance model and the switching time model. As verified by the published data, the analytical DC/capacitance model provides an accurate prediction. Based on the analytical model, the threshold voltage of an a-Si:H TFT is proportional to the deep state density and the switching time of the TFT-inverter is dependent on the tail state density. >

A compact threshold voltage model for gate misalignment effect of DG FD SOI nMOS devices considering fringing electric field effects

This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted silicon-on-insulator nMOS devices using a compact model considering the fringing electric field effect, biased at zero-bias V/sub DS/. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric field effect in the nongate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the two-dimensional simulation results.

A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability

This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.