Shengdong Zhang

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFTs.

Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass

A novel low temperature poly-Si (LTPS) TFT technology called the ultra-thin elevated channel TFT (UT-ECTFT) technology is proposed. The devices fabricated using this technology have an ultra-thin channel region (300 /spl Aring/) and a thick drain/source region (3000 /spl Aring/). The ultra-thin channel region is connected to the heavily doped thick drain/source region through a lightly doped overlapped region. The ultra-thin channel region is used to obtain a low grain-boundary trap density in the channel, and the overlapped lightly doped region provides an effective way for electric field spreading at the drain, thereby reducing the electric field there significantly. With the low grain-boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are obtained in the UT-ECTFT. Moreover, this technology provides complementary LTPS TFTs with more than two times increase in on-current and 3.5 times reduction in off-current compared to conventional thick channel LTPS TFTs.

Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices

A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.

Solution-Processed MoS2/Organolead Trihalide Perovskite Photodetectors

Integration of organic/inorganic hybrid perovskites with metallic or semiconducting phases of 2D MoS2 nanosheets via solution processing is demonstrated. The results show that the collection of charge carriers is strongly dependent on the electronic properties of the 2D MoS2 with metallic MoS2 showing high responsivity and the semiconducting phase exhibiting high on/off ratios.

3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies

This paper describes a method to integrate non-planar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis

High-Performance Transparent AZO TFTs Fabricated on Glass Substrate

High-performance transparent low-temperature top-gate type aluminum doped zinc oxide (AZO) thin-film transistors (TFTs) (<i>W</i>/<i>L</i>=100 or 10 μm) are successfully fabricated on glass substrate. All the process temperature is below 100°C. For <i>VG</i>=-2 to 5 V, the TFTs using sputtering deposit AZO layer at room temperature as channel layer exhibits excellent properties, such as a saturation mobility μ<i>s</i> of 285 cm²/V·s, a linear field effect mobility μ<i>l</i> of 143 cm²/V·s, a threshold voltage <i>Vth</i> of 0.9 V, a steep subthreshold swing of 108 mV/decade, a low off-state current value <i>I</i>_off of 5×10^-13 A, a high ON/OFF ratio of 2×10⁹ and a high transmittance of 82.5%. The results highlight that excellent device performance can be realized in AZO TFTs. Note that this is the best performance of AZO TFT ever reported.

A novel self-aligned double-gate TFT technology

In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate (TG) and bottom-gate (BG) is realized by a noncritical chemical-mechanical polishing (CMP) step. An ultrathin channel and a thick source/drain, that allow better device performance and lower source/drain resistance, are also automatically achieved. N-channel poly-Si TFTs are fabricated with maximum processing temperature below 600/spl deg/C. Metal induced unilateral crystallization (MIUC) is used for poly-Si grain size enhancement. The fabricated SADG TFT exhibits symmetrical bidirectional transfer characteristics when the polarity of source/drain bias is interchanged. The on-current under double-gate operation is more than two times the sum of that under TG and BG operation.