James C. Chen

An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique

In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.0l fF or 10 aF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. The measurement itself is also simple; only a DC current meter is required. We have applied this technique to extract various interconnect geometry capacitances, including the capacitance of a single Metal 2 over Metal 1 crossing, for an industrial double metal process.

Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal

It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate.<<ETX>>

Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 /spl mu/m, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well.

Two modes of ligand binding in maltose-binding protein of Escherichia coli. Functional significance in active transport.

In the preceding two papers (Hall, J. A., Gehring, K., and Nikaido, H. (1997) J. Biol. Chem.272, 17605–17609; Hall, J. A., Thorgeirson, T. E., Liu, J., Shin, Y.-E., and Nikaido, H. (1997) J. Biol. Chem.272, 17610–17614), we showed that ligands that bind to theEscherichia coli maltose-binding protein (MBP) without producing the closure of its two lobes are not transported into the cytoplasm. Here, we examine various combinations of ligands, MBPs, and membrane-associated transporters, by utilizing reconstituted proteoliposomes, right side-out membrane vesicles, and intact cells. Closed forms of wild type MBP, complexed with maltose or maltodextrins, interacted with wild type transporter complex to stimulate the hydrolysis of ATP by MalK ATPase located on the other side of the membrane, as shown earlier for the maltose-MBP complex (Davidson, A. L., Shuman, H. A., and Nikaido, H. (1992) Proc. Natl. Acad. Sci. U. S. A. 89, 2360–2364). In contrast, open forms of liganded MBPs, such as the complex containing wild type MBP and reduced, oxidized, or cyclic maltodextrins or the complex containing the mutant MBP MalE254 and unmodified maltodextrins, did not stimulate ATP hydrolysis, suggesting that the proper interaction between the ligand-MBP complex and the external surface of the transporter requires the former to be in the closed conformation. However, when a mutant transporter containing MalG511 was used, the already significant basal level of ATP hydrolysis was further stimulated not only by ligand MBPs in the closed form but also by those in the open form (except that containing β-cyclodextrin), data suggesting that the mutant transporter does not always require the closed MBP complex presumably because of its exceptionally strong affinity to MBP, described earlier (Dean, D. A., Hor, L.-I., Shuman, H. A., and Nikaido, H. (1992)Mol. Microbiol. 6, 2033–2040). Furthermore, this mutant transporter was able to transport reduced maltodextrin, and cells expressing the transporter were able to grow by using reduced maltodextrin, if the periplasmic concentrations of MBP were kept low so as not to inhibit the transport process.

E-T based statistical modeling and compact statistical circuit simulation methodologies

A new statistical parameter extraction methodology which translates actual process variations into SPICE model parameter variations is presented. This methodology uses E-T data to extract SPICE model parameters and guarantees that its extraction results match measured variations. We have applied this methodology to an industrial 0.5 /spl mu/m process. Excellent, overall I-V curve fit for multiple device geometries is achieved. A compact statistical circuit design technology that improves upon the typical/worst/best case methodology is also presented.

A simple method for on-chip, sub-femto Farad interconnect capacitance measurement

In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current meter is required. Furthermore, the extraction methodology employs a self-checking algorithm to verify that the extracted capacitance value is consistent and accurate. The technique is demonstrated by extracting the capacitance of a single crossover between a Metal 1 line and a Metal 2 of 0.44 fF. The resolution limit is dominated by the matching of the minimum sized transistors used for the test structure. We estimate this resolution limit to be about 0.03 fF.

Direct sampling methodology for statistical analysis of scaled CMOS technologies

The continued scaling of CMOS technologies introduces new difficulties to statistical circuit analysis and invalidates many of the methodologies developed earlier. The analysis of device parameter distributions reveals multiple sources of parameter correlations, some of which exhibit mutually opposing trends. We found that applying principal component analysis (PCA) to such heterogeneous statistical data may lead to confounding of data and result in underestimation of the total parameter variance. This imposes considerable constraints on the use of several methods of statistical circuit analysis based on PCA. Also the highly nonlinear relationships between the device parameters become more pronounced and cannot be approximated as linear even in the differential range. As a result, the response surface models based on the linear expansion of the performance variable around the nominal point of the device model parameters may lead to significant prediction errors. To address these difficulties, we propose a conceptually simple and accurate approach of direct sampling that treats the extracted SPICE parameter sets and their physical locations as an inseparable set and thus bypasses the dangerous stage of statistical inferences. We illustrate the methodology by applying it to the statistical analysis of a production CMOS process.

Realistic worst-case SPICE file extraction using BSIM3

In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these block are determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gates implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance.

A statistical performance simulation methodology for VLSI circuits

A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.