Bruce W. McGaughy

Design tools for reliability analysis

Recent progress in EDA tools allows IC designs to be accurately verified with consequent improvements in yield and performance through reduced guard bands. This paper present a tools perspective, including the primary effects such as HCI, NBTI and EM for which EDA tools are available, types of tools (dynamic simulation vs. static rule checking) and necessary reliability infrastructure and flows that have been working in practice. Finally, developing areas and future opportunities are addressed

An efficient method for terminal reduction of interconnect circuits considering delay variations

This paper proposes a novel method to efficiently reduce the terminal number of general linear interconnect circuits with a large number of input and/or output terminals considering delay variations. Our new algorithm is motivated by the fact that VLSI interconnect circuits have many similar terminals in terms of their timing and delay metrics due to their closeness in structure or due to mathematic approximation using meshing in finite difference or finite element scheme during the extraction process. By allowing some delay tolerance or variations, we can reduce many similar terminals and keep a small number of representative terminals. After terminal reduction, traditional model order reduction methods can achieve more compact models and improve simulation efficiency. The new method, TermMerg, is based on the moments of the circuits as the metrics for the timing or delay. It then employs singular value decomposition (SVD) method to determine the optimum number of clusters based on the low-rank approximation. After this, the K-means clustering algorithm is used to cluster the moments of the terminals into different clusters. Experimental results on a number of real industry interconnect circuits demonstrate the effectiveness of the proposed method.

ETBR: extended truncated balanced realization method for on-chip power grid network analysis

In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the before the simulation. Different from the (improved) extended Krylov subspace methods EKS/IEKS [15, 2], ETBR performs fast truncated balanced realization on response Grammian to reduce the original system with the similar computation costs of EKS. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation of input signals by fast Fourier transformation. As a result, ETBR is more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. ETBR also shows similar computation costs of EKS and less memory consumption than EKS.

Second-Order Balanced Truncation for Passive-Order Reduction of RLC K Circuits

In this paper, we propose a novel model-order reduction (MOR) approach, second-order balanced truncation (BT) for passive-order reduction (SBPOR), which is the first second-order BT method proposed for passive reduction of RLCK circuits. By exploiting the special structure information in the circuit formulation, second-order Gramians are defined based on a symmetric first-order realization in descriptor from. As a result, SBPOR can perform the traditional balancing with passivity-preserving congruency transformation at the cost of solving one generalized Lyapunov equation. Owing to the second-order formulation, SBPOR also preserves the structure information inherent to RLCK circuits. We further propose, second-order Gramian approximation (SOGA) version of SBPOR , to mitigate high computational cost of solving Lyapunov equation. Experimental results demonstrate that SBPOR and SOGA are globally more accurate than the Krylov subspace based approaches.

An efficient terminal and model order reduction algorithm

The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the recently proposed terminal reduction method, SVDMOR [P. Feldmann, F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, in: Proceedings of the International Conference on Computer Aided Design (ICCAD), 2004, pp. 88-92]. But different from SVDMOR, the new method considers higher order moment information for terminal responses during the terminal reduction and separately applies singular value decomposition (SVD) on both input and output terminals for low-rank approximations. This is in contrast to the SVDMOR method where input and output terminal responses are approximated by SVD at the same time, which can lead to large errors when the numbers of inputs and outputs are quite different. We analyze the passivity requirements for SVD-based terminal and model order reduction and show that the combined passive terminal and MOR using SVD method will not lead an effective terminal reduction in general. Our experimental results show that the proposed ESVDMOR method outperforms the SVDMOR method in terms of accuracy for the same reduced model sizes when the numbers of input and output terminals are quite different.

An essentially non-oscillatory (ENO) high-order accurate adaptive table model for device modeling

Modern analytical device models become more and more complicated and expensive to evaluate in circuit simulation. Interpolation based table look-up device models become increasingly important for fast circuit simulation. Traditional table model trades accuracy for speed and is only used in fast-Spice simulators but not good enough for prime-time Spice simulators such as SPECTRE. We propose a novel table model technology that uses high-order essentially non-oscillatory (ENO) polynomial interpolation in multi-dimensions to guarantee smoothness in multi-dimensions and high accuracy in approximating i -- v/q --v curves. An efficient transfinite blending technique for the reconstruction of multi-dimensional tables is used. Interpolation stencil is adaptively determined by automatic accuracy control. The method has been proved to be superior to traditional ones and successfully applied in Spectre and Ultrasim for simulating digital, analog, RF, and mixed-signal circuits.

TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits

In this paper, a novel method to efficiently reduce the terminal number of general linear-interconnect circuits with a large number of input or output terminals considering delay uncertainty is proposed. Our new algorithm is motivated by the fact that terminal reduction can lead to a more compact order-reduced model and the observation that very large-scale integration interconnect circuits have many similar terminals in terms of their timing and delay metrics due to their closeness in structure or due to the mathematical discretization using meshing in finite-difference or finite-element scheme during the extraction process. The new method, called TermMerg ( Proc. ICCAD, p. 821, 2005), is based on the moments of the circuits as the metrics for the timing or delay. It then employs a singular-value-decomposition (SVD) method to determine the best number of clusters based on the low-rank approximation. After this, the -means clustering algorithm is used to cluster the moments of the terminals into the different clusters. The proposed method can work with any passive-model order reduction and ensure the passive models. In contrast, we show that singular value decomposition model order reduction (SVDMOR) does not generate passive models in general. Passivity enforcement in SVDMOR will significantly hamper the terminal-reduction effectiveness. Experimental results on a number of real industry interconnect circuits demonstrate the effectiveness of the proposed method and show also that the proposed method is more accurate than SVDMOR when the used moment matrix does not give good terminal correlations.

An Extended SVD-based Terminal and Model Order Reduction Algorithm

The paper proposes a new combined terminal and model order reduction method for compact modeling of interconnect circuits. The new method extends the existing SVDMOR method by using higher order moment information for terminal responses during the terminal reduction and by applying separate SVD low-rank approximations on input and output terminals respectively. This is in contrast to SVDMOR method where input and output terminal responses are SVD approximated at the same time, which can lead to large error when the numbers of inputs and outputs are quite different. We analyze the passivity requirement for combined terminal and model order reduction and show the passivity enforcement may significantly hamper the terminal reduction effects. We also improve the computation efficiency of SVDMOR. Our experimental results show that ESVDMOR outperforms the SVDMOR in terms of accuracy for the similar reduced model sizes in a number of interconnect circuits when the input and output terminals are different

DeMOR: decentralized model order reduction of linear networks with massive ports

Model order reduction is an efficient technique to reduce the system complexity while producing a good approximation of the input-output behavior. However, the efficiency of reduction degrades as the number of ports increases, which remains a long-standing problem. The reason for the degradation is that existing approaches are based on a centralized framework, where each input-output pair is implicitly assumed to be equally interacted and the matrix-valued transfer function has to be assumed to be fully populated. In this paper, a decentralized model order reduction scheme is proposed, where a multi-input multi-output (MIMO) system is decoupled into a number of subsystems and each subsystem corresponds to one output and several dominant inputs. The decoupling process is based on the relative gain array (RGA), which measures the degree of interaction of each input-output pair. Our experimental results on a number of interconnect circuits show that most of the input- output interactions are usually insignificant, which can lead to extremely compact models even for systems with massive ports. The reduction scheme is very amenable for parallel computing as each decoupled subsystem can be reduced independently.

Passive Modeling of Interconnects by Waveform Shaping

In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models passive for infinite frequencies, which is difficult and inefficient using state-of-the-art optimization based methods for circuits with many terminals and operating in wideband frequency ranges, the new method works on the signal waveform driving reduced models. It slightly shapes the waveforms of the signal such that the resulting signal spectra are band limited to the frequency range in which the reduced system is passive. As a result, the reduced models only need to be band-limited passive (also called conditionally passive), which can be achieved much easier than traditional passivity for a reduced system, especially for ones with many terminals or requiring wide band accuracy (more poles). We propose to use spectrum truncation via FFT/IFFT and low-pass filter based approaches for transient waveform shaping processing. We analyze the delay and distortion effects caused by using low-pass filters and propose methods to mitigate the two effects. Experimental results on several interconnect circuits demonstrate the effectiveness of the proposed methods