James E. Stine

A standard cell library for student projects

A standard-cell library for MOSIS scaleable CMOS rules has been developed. It is intended for use with Synopsys Design Compiler, Cadence Silicon Ensemble, and Cadence Virtuoso or Magic. The library is targeted for the AMI 0.5 /spl mu/m process, which currently offers the smallest feature size in the MOSIS educational program. The library also includes I/O pad cells and fully places and routes a padframe if desired. All steps in the design flow are fully automated with only three scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology. To customize and run these three scripts, for a given design, typically takes less than five minutes, since all details are transparent to the students, allowing them to focus on the design instead of worrying about the tools.

Reduced power dissipation through truncated multiplication

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits.

Variations on truncated multiplication

Truncated multiplication can be used to significantly reduce the power dissipation for applications that do not require correctly-rounded results. This paper presents an efficient method for truncated multiplication called hybrid-correction truncation that utilizes the advantages of two previous methods to obtain lower average and maximum absolute error. Comparisons are presented contrasting power, area, and delay for all three methods compared to standard parallel multipliers. Estimates indicate that hybrid truncated multipliers dissipate slightly less power and consume slightly less area than previous methods for truncated multiplication. In addition, utilization of the hybrid truncation method can provide a method for altering the implementation within certain limits to meet a given precision.

A framework for high-level synthesis of system on chip designs

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.

A combined two's complement and floating-point comparator

This paper presents the design of a combined twos complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both operand types into one unit, while still maintaining low area and high speed. The comparator design uses a novel magnitude comparator with logarithmic delay, plus additional logic to handle both twos complement and floating point operands. The comparator fully supports 32-bit and 64-bit floating-point comparisons, as defined in the IEEE 754 standard, as well as 32-bit and 64-bit twos complement comparisons. Area and delay estimates are presented for designs implemented in AMI C5N 0.5 /spl mu/m CMOS technology.

Constant addition utilizing flagged prefix structures

The role of addition and subtraction in digital systems is sometimes complicated due to the arrival of certain operands occurring at different times. For example, floating-point arithmetic typically requires the exponent logic to wait until an output is received from post-normalization. Previously, logic designers have resorted to the use of conditional sum and carry-select adders to make their design efficient. Recently, a new technique has been proposed that utilizes the concept of flagged prefix addition. Flagged prefix addition utilizes the parallel-prefix adder and slightly modifies it to yield a new adder that is capable of adding A+B or A+B+1. Moreover, alterations to the logic can easily be made to allow difference operations to occur as well. The paper presents an extension to flagged prefix addition to allow an arbitrary number to be added to the logic. Results are shown for several designs in AMI C5N 0.5 /spl mu/m technology.

Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation

Truncated multiplication can be used to significantly reduce power dissipation for applications that do not require correctly rounded results. This paper presents a power efficient method for designing floating point multipliers that can perform either correctly rounded IEEE compliant multiplication or truncated multiplication, based on an input control signal. Compared to conventional IEEE floating point multipliers, these multipliers require only a small amount of additional area and delay, yet provide a significant reduction in power dissipation for applications that do not require IEEE compliant results.

Parallel programmable finite field GF (2/sup m/) multipliers

Block (cyclic) channel coding standards for third generation cellular networks require the implementation of high-performance burst-error detection and correction algorithms. Galois field (GF) arithmetic is commonly used in this architecture for encoding and decoding error codes, however, many architectures still do not support dedicated functional units. This paper presents the design of a generic parallel finite-field GF (2/sup m/) multiplier targeted at DSP and embedded processors. As opposed to previous research, this design has the ability to utilize different primitive polynomials as an input, thereby, being able to be programmable. Moreover, a design is presented that is a combined binary and finite-field GF (2/sup m/) multiplier. Area, delay, and power dissipation results are presented from several ASIC libraries.

Modified booth truncated multipliers

Truncated multiplication provides an efficient method for reducing the power dissipation and area of rounded parallel multipliers in digital signal processing systems. With this technique, the products of parallel multipliers are rounded to a shorter word size and the least-significant columns of the multiplication matrix are not used. This technique provides significant savings in terms of power dissipation for unsigned multiplication. Although previous implementations involved unsigned and signed array and tree multipliers, this technique can be equally applied to multiplication using Booth-encoding. This paper presents the design and implementation of parallel and truncated multipliers that use Booth-encoding and compressors for signed multiplication. Initial estimates indicate that truncated parallel multipliers dissipate less power than standard parallel multipliers for operand sizes of 16 bits.

A hybrid Ling carry-select adder

Hybrid adders, combining a sparse carry-lookahead tree and a carry-select output stage are a well-known implementation form of high-speed adders. In this paper, a hybrid Ling carry-select adder is presented. It is shown how a carry-select output stage can be used to eliminate the entire conversion of all pseudo-carries. The adder is implemented in enhanced multiple output domino logic (EMODL). A technique is presented to avoid false discharge paths, which present impairment to EMODL, in the sum selection multiplexer.