Michael J. Schulte

Approximating elementary functions with symmetric bipartite tables

This paper presents a high-speed method for function approximation that employs symmetric bipartite tables. This method performs two parallel table lookups to obtain a carry-save (borrow-save) function approximation, which is either converted to a twos complement number or is Booth encoded. Compared to previous methods for bipartite table approximations, this method uses less memory by taking advantage of symmetry and leading zeros in one of the two tables. It also has a closed-form solution for the table entries, provides tight bounds on the maximum absolute error, and can be applied to a wide range of functions. A variation of this method provides accurate initial approximations that are useful in multiplicative divide and square root algorithms.

The Symmetric Table Addition Method for Accurate Function Approximation

This paper presents a high-speed method for computing elementary functions using parallel table lookups and multi-operand addition. Increasing the number of tables and inputs to the multi-operand adder significantly reduces the amount of memory required. Symmetry and leading zeros in the table coefficients are used to reduce the amount of memory even further. This method has a closed-form solution for the table entries and can be applied to any differentiable function. For 24-bit operands, it requires two to three orders of magnitude less memory than conventional table lookups.

Symmetric bipartite tables for accurate function approximation

The paper presents a methodology for designing bipartite tables for accurate function approximation. Bipartite tables use two parallel table lookups to obtain a carry-save (borrow-save) function approximation. A carry propagate adder can then convert this approximation to a twos complement number or the approximation can be directly Booth encoded. Our method for designing bipartite tables, called the Symmetric Bipartite Table Method, utilizes symmetry in the table entries to reduce the overall memory requirements. It has several advantages over previous bipartite table methods in that it: (1) provides a closed form solution for the table entries; (2) has right bounds on the maximum absolute error; (3) requires smaller table lookups to achieve a given accuracy; and (4) can be applied to a wide range of functions. Compared to conventional table lookups, the symmetric bipartite tables presented are 15.0 to 41.7 times smaller when the operand size is 16 bits and 99.1 to 273.9 times smaller when the operand size is 24 bits.

Reduced power dissipation through truncated multiplication

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits.

A family of variable-precision interval arithmetic processors

Traditional computer systems often suffer from roundoff error and catastrophic cancellation in floating point computations. These systems produce apparently high precision results with little or no...Traditional computer systems often suffer from roundoff error and catastrophic cancellation in floating point computations. These systems produce apparently high precision results with little or no indication of the accuracy. This paper presents hardware designs, arithmetic algorithms, and software support for a family of variable-precision, interval arithmetic processors. These processors give the programmer the ability to detect and, if desired, to correct implicit errors in finite precision numerical computations. They also provide the ability to solve problems that cannot be solved efficiently using traditional floating point computations. Execution time estimates indicate that these processors are two to three orders of magnitude faster than software packages that provide similar functionality.

Combined unsigned and two's complement squarers

Squaring is an important operation in digital signal processing applications. For several applications, a significant reduction in area, delay, and power consumption is achieved by performing squaring using specialized squarers, instead of multipliers. Although most previous research on parallel squarers focuses on the design of unsigned squarers, squaring of twos complement numbers is also often required. This paper presents the design of parallel squarers that perform either unsigned or twos complement squaring, based on an input control signal. Compared to unsigned parallel squarers, these squarers require only a small amount of additional delay and area.

The sandbridge SB3011 SDR platform

This paper describes the Sandbridge Sandblaster real-time software defined radio platform. Specifically we describe the SB301I system on a chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. All results presented are from completely implemented systems from RF through baseband

High-speed inverse square roots

Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing inverse square roots. This method uses a table lookup, operand modification, and multiplication to obtain an initial approximation to the inverse square root. This is followed by a modified Newton-Raphson iteration, consisting of one square, one multiply-complement, and one multiply-add operation. The initial approximation and Newton-Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. Application of this method is illustrated through the design of an inverse square root unit operands in the IEEE single precision format. An implementation of this unit with a 4-layer metal, 2.5 Volt, 0.25 micron CMOS standard cell library has a cycle rime of 6.7 ns, an area of 0.41 mm/sup 2/, a latency of five cycles, and a throughput of one result per cycle.

Design alternatives for barrel shifters

Barrel shifters are often utilized by embedded digital signal processors and general-purpose processors to manipulate data. This paper examines design alternatives for barrel shifters that perform the following functions: shift right logical, shift right arithmetic, rotate right, shift left logical, shift left arithmetic, and rotate left. Four different barrel shifter designs are presented and compared in terms of area and delay for a variety of operand sizes. This paper also examines techniques for detecting results that overflow and results of zero in parallel with the shift or rotate operation. Several Java programs are developed to generate structural VHDL models for each of the barrel shifters. Synthesis results show that data-reversal barrel shifters have less area and mask-based data-reversal barrel shifters have less delay than other designs. Mask-based data-reversal barrel shifters are especially attractive when overflow and zero detection is also required, since the detection is performed in parallel with the shift or rotate operation.

A combined 16-bit binary and dual Galois field multiplier

Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit twos complement or unsigned multiplication, or two independent 8-bit GF(2/sup 8/) multiplications in SIMD fashion. The combined multiplier is designed by modifying a conventional binary tree multiplier. It uses a novel wiring methodology to provide two simultaneous GF(2/sup 8/) multiplies with a minor impact on area and delay. Two alternatives for the multiplier design are presented. Area and delay estimates indicate that compared to a conventional binary tree multiplier, the combined multiplier has roughly 6% more delay and 23% more area.