James O. Bondi

Integrating a misprediction recovery cache (MRC) into a superscalar pipeline

In modern processors, deep pipelines couple with superscalar techniques to allow each pipe stage to process multiple instructions. When such a pipe must be pushed and refilled, as when predicted program flow beyond a branch is subsequently recognized as wrong, the temporary performance loss is significant. While modern branch target buffer (BTB) technology makes this flush/refill penalty fairly rare, the penalty that accrues from the remaining branch mispredictions is a serious impediment to even higher processor performance. Advanced mechanisms that can reduce this residual misprediction penalty can be of enormous value in future microprocessor designs. One promising new mechanism, the Misprediction Recovery Cache (MRC) is proposed previously. In this paper, we focus especially on MRC integration into existing pipelines.

A microcoded real-time executive for numeric support nodes distributed within embedded networks

The mix of nodes within heterogeneous embedded networks typically includes some highly specialized, numerically oriented nodes particularly adept at efficient manipulation of regularly structured, multi-element array operands. Such “Array Processing” (AP) nodes usually serve other more general-purpose (GP) nodes. Local node-level control of each AP is maintained by a microcoded AP-resident executive program (APX). The APX is carefully microcoded and tuned to minimize overhead incurred by the computation-or-throughput-intensive tasks using or sharing AP resources.

Integrating hierarchical test benches into an evolving VHDL design environment

Flexible, hierarchical test benches are developed naturally as part of the normal model development process and support VHDL, WAVES, and company-proprietary standards. The integration of these tool-automated VHDL test benches is described. In TI-Microelectronics, automated development of VHDL test benches and integration of test bench development into the VHDL modeling process are being employed successfully. The novel hierarchical structuring technique described integrates automated VHDL test bench capabilities with the historical TI proprietary design environment.<<ETX>>

Architectural support of fine-grained secure computing

An architecture especially adept at security support is outlined. The architectures fundamental information unit is a two-tuple, or ordered pair, consisting of a datum word and an associated security tag. As an atomic information unit, the two-tuple moves around through the architecture in unison as processing proceeds. a security subprocessor always operates on a security tag in synchrony with a fairly ordinary data subprocessors operation on the associated datum word. The coupled subprocessors provide the overall architecture with efficient, multilevel-secure access control and flow control. The proposed architecture represents the advancement of security technology along a unique combination of three fronts: (1) direct hardware support, (2) fine-grained-to-the-word mediation, and (3) optimal (minimal) result classification.<<ETX>>