James Otto Nicholson

The RISC system/6000 SMP system

The IBM RISC System/6000 Symmetric Multiprocessor is a new addition to IBMs successful line of RISC-based commercial servers. It utilizes balanced system design principles and introduces new levels of function and scalability. This paper will focus on design issues and technical attributes pertinent to achieving these goals.

New micro channel features

Three features of the Micro Channel architecture are discussed. These features broaden the characteristics of that architecture to support advanced I/O devices or systems. These new features are a streaming data procedure (including 64-b transfers), address and data parity, and synchronous exception signaling. Streaming data is a procedure that provides the ability to transfer multiple data cycles within one bus envelope. The procedure distributes the device selection overhead across the total packet, nearly doubling (for 32 b) or quadrupling (for 64 b) the performance capability of the Micro Channel bus. Address and data parity are provided to improve the data integrity characteristics of the Micro Channel architecture. These mechanisms are particularly well suited to detecting typical errors, such as card seating problems, power disturbance, and electromagnetic interference. The Micro Channel architecture provides for exception signaling with the CHCK signal. The enhancements use previously reserved pins on the Micro Channel bus and retain compatibility with existing card and system board designs.<<ETX>>