Sudhir Dhawan

POWER2: next generation of the RISC System/6000 family

Since its announcement, the IBM RISC System/6000@ processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.

IBM second-generation RISC machine organization

A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously.<<ETX>>

Design of self-checking sequential machines

The authors present the design of self-checking sequential machines using standard memory elements, i.e. D, T, or JK flip-flops. The design approach involves cascading the three parts of a sequential machine, i.e. excitation, memory elements, and the output circuit. Parity is used to detect and transmit errors from one part to the next. The conditions for testing D, T, and JK flip-flops and for transmitting errors from their inputs to their outputs are presented; these are shown to exist in normal operation when the design procedure is used. SR flip-flops are found not to have the properties necessary for designing self-checking sequential machines. >

The POWER2 processor

The IBM POWER2 is a second-generation, multi-chip superscalar RISC processor. It provides dual branch processing units, dual fixed-point units, dual floating-point units, and advanced superscalar techniques. It is capable of executing 6 instructions per cycle and 8 operations per cycle. The processor also provides large caches, long cache lines, and high bandwidth buses to memory and I/O.<<ETX>>

Design of self-checking iterative networks

The relevant definitions are given and a model of self-checking iterative network is presented. A general combinational circuit was developed that is totally self-checking and can detect an error on the input code lines and transmit the error to the output code lines. Thus, an error generated in a cell is transmitted from cell to cell until the last cell is reached. The error, and fault that generated it, can be detected by the checker at the last cell, which can also be made self-checking. The added redundancy increases the amount of logic required to realize the circuit, and the increase depends on the circuit being realized. If z is the number of output code lines for a general cell, a rough estimate of the percent increase in circuitry is 1/z*100. >