James W. Conary

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology

The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor Vth, improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM VMIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2nd-generation FinFET transistors.

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry

A 0.6-1.1 V, 84 Mb pipelined SRAM array design implemented in 14 nm FinFET CMOS technology is presented. Two array architectures featuring a high-density 0.0500 μm 2 6T SRAM bitcell and a 0.0588 μm 2 6T SRAM bitcell targeting low voltage operation are detailed. The high-density array design reaches 2.7 GHz at 1.1 V with 14.5 Mb/mm 2 bit density, while the low voltage optimized array can operate at 0.6 V, 1.5 GHz under typical process conditions. A capacitive charge-share transient voltage collapse write-assist circuit (CS-TVC) enables a 24% reduction in write energy compared to previous techniques by eliminating bias currents during operation. Technology and assist co-optimization enable 50 mV reduction in V MIN and a 1.81× increase in density over a 22 nm design.

A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB

A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu/m Intel(R) Pentium(R) III processor family. The cache tile is stepped from 1 to 8 times to form implementations from 256 KB to 2 MB. Each tile is a self-contained cache delivering a line of 32 B every 2 clock cycles at 1.0 GHz. A charge-share data sense technique overlaps the data and tag array accesses for reduced latency at lower power. Modular tiled cache design also achieves low power through hierarchical power management and reduced test time through PBIST (programmable built in self test).