Satyanand Nalam

Analyzing static and dynamic write margin for nanometer SRAMs

This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.

Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T

This paper describes a 5-transistor (5T) SRAM bitcell that uses a novel asymmetric sizing approach to achieve increased read stability. Measurements of a 32 kb 5T SRAM in a 45nm bulk CMOS technology validate the design, showing read functionality below 0.5V. The 5T bitcell has lower write margin than the 6T, but measurements of the 45nm 5T array confirm that a write assist method restores comparable writability with a 6T down to 0.7 V.

5T SRAM With Asymmetric Sizing for Improved Read Stability

Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due to a complex trade-off space involving stability, performance, power, and area. Local and global variation make SRAM design even more challenging. We present a 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and to provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare the 5T with the conventional 6T and the 8T and show how it can be a flexible, intermediate alternative between the two. We also investigate single-ended sensing for the 5T. Finally, we present measurement results in a 45 nm test chip that demonstrate the functionality of the 5T. Through a combination of write assists, the 5T can demonstrate comparable writability down to 0.7 V, while showing no read errors down to 0.5 V.

Improving SRAM Vmin and yield by using variation-aware BTI stress

We propose a novel method that exploits BTI to partially offset variation and thus improve SRAM Vmin and yield. We show correlation between a bitcells power-up state and its static noise margin. By applying stress with periodic re-power-up, device mismatch can be compensated by BTI induced changes. The proposed method has no extra design and area cost. It can be applied during burn-in test to offset manufacturing variation and/or used during the lifetime of the chip to offset variation from real-time aging and hence continue to improve the margins. Simulations in 45nm show that write, read, and hold Vmin at 6σ can be reduced by 128, 75, and 91 mV, respectively. Measurements from a 16Kb 45nm SRAM demonstrate the improvement of Vmin and yield.

Dynamic write limited minimum operating voltage for nanoscale SRAMs

Dynamic stability analysis for SRAM has been growing in importance with technology scaling. This paper analyzes dynamic writability for designing low voltage SRAM in nanoscale technologies. We propose a definition for dynamic write limited VMIN. To the best of our knowledge, this is the first definition of a VMIN based on dynamic stability. We show how this VMIN is affected by the array capacity, the voltage scaling of the word-line pulse, the bitcell parasitics, and the number of cycles prior to the first read access. We observe that the array can be either dynamically or statically write limited depending on the aforementioned factors. Finally, we look at how voltage-bias based write assist techniques affect the dynamic write limited VMIN.

Limits of bias based assist methods in nano-scale 6T SRAM

Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRAM arrays beyond 65nm will increasingly rely on assist methods to overcome the functional limitations imposed by increased variation, reduced overdrive and the inherent read stability/write margin trade off. Factors such as reliability, leakage and data retention establish the boundary conditions for the maximum voltage bias permitted for a given circuit assist approach. These constraints set an upper limit on the potential yield improvement that can be obtained for a given assist method and limit the minimum operation voltage (Vmin). By application of this set of constraints, we show that the read assist limit contour (ALC) in the margin/delay space can provide insight into the ultimate limits for the nano-scale CMOS 6T SRAM.

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation

This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area.

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers

SRAM design in scaled technologies requires knowledge of phenomena at the process, circuit, and architecture level. Decisions made at various levels of the design hierarchy affect the global figures of merit (FoMs) of an SRAM, such as, performance, power, area, and yield. However, the lack of a quick mechanism to understand the impact of changes at various levels of the hierarchy on global FoMs makes an accurate assessment of SRAM design innovations difficult. Thus, we introduce Virtual Prototyper (ViPro), a tool that helps SRAM designers explore the large design space by rapidly generating optimized virtual prototypes of complete SRAM macros. It does so by allowing designers to describe the SRAM components with varying levels of detail and by incorporating them into a hierarchical model that captures circuit and architectural features of the SRAM to optimize a complete prototype. It generates base-case prototypes that provide starting points for design space exploration, and assesses the impact of process, circuit, and architectural changes on the overall SRAM macro design.

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

A designers intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designers knowledge and separate it from the technology-specific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm.

Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories

Conventional strobed sense amplifiers (SA) have a fixed offset that dictates the minimum BL droop required during a memory read. BL droop is the major component of memory read delay and energy. In this paper we propose a novel non-strobed sensing scheme that can tradeoff BL droop with SA delay, allowing a memory to operate with lower BL droop, and thus lower energy. We demonstrate the sensing scheme on an 16KB SRAM. Lower BL swing results in 15% lower energy per read operation. The performance penalty due to higher SA delay is avoided by pipelining the SA delay into the next clock cycle. Thus, in addition to lower energy per read, a pipelined non-strobed SRAM is 52% faster than a conventional strobed SRAM and 26% faster than a pipelined strobed SRAM. This is the first work that demonstrates how BL droop can be traded-off with SA delay, enabling lower energy operation. We show the concept, circuit implementation, and simulation results in a commercial 45nm technology node.