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James W. Keeley

Honeywell

Publication

Featured researches published by James W. Keeley.

Archive | 1984

Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization

James W. Keeley; Thomas F. Joyce

Archive | 1985

Resilient bus system

George J. Barlow; James W. Keeley

Archive | 1990

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

George J. Barlow; James W. Keeley; Richard A. Lemay; Jian-Kuo Shen; Robert V. Ledoux; Thomas F. Joyce; Richard P. Kelly; Robert C. Miller

Archive | 1988

Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement

James W. Keeley

Archive | 1982

Multilevel cache system with graceful degradation capability

James W. Keeley; Edwin P. Fisher; John L. Curley

Archive | 1986

Shared interface apparatus for testing the memory sections of a cache unit

James W. Keeley

Archive | 1989

Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing

George J. Barlow; Elmer W. Carroll; James W. Keeley; Wallace A. Martland; Victor M. Morganti; Arthur Peters; Richard C. Zelley

Archive | 1987

Cache resiliency in processing a variety of address faults

George J. Barlow; James W. Keeley; Chester M. Nibby

Archive | 1986

Read in process memory apparatus

James W. Keeley; George J. Barlow

Archive | 1983

Enable/disable control checking apparatus

James W. Keeley; Robert V. Ledoux; Virendra S. Negi

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