Jan Bogaerts

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525/spl times/525 pixels measuring 7.5 /spl mu/m/spl times/10 /spl mu/m, and is fabricated in a 0.5-/spl mu/m CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range.

Total dose and displacement damage effects in a radiation-hardened CMOS APS

A 512/spl times/512 CMOS active pixel sensor (APS) was designed and fabricated in a standard 0.5-/spl mu/m technology. The radiation tolerance of the sensor has been evaluated with Co-60 and proton irradiation with proton energies ranging from 11.7 to 59 MeV. The most pronounced radiation effect is the increase of the dark current. However, the total ionizing dose-induced dark current increase is orders of magnitude smaller than in standard devices. It behaves logarithmically with dose and anneals at room temperature. The dark current increase due to proton displacement damage is explained in terms of the nonionizing energy loss of the protons. The fixed pattern noise does not increase with total ionizing dose. Responsivity changes are observed after Co-60 and proton irradiation, but a definitive cause has not yet been established.

Time-Delay-Integration Architectures in CMOS Image Sensors

Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum efficiency specification in the architecture definition. Moderate spatial and temporal oversamplings are combined to achieve near charge-coupled device (CCD) class performances, resulting in an acceptable design complexity. Finally, CCD and CMOS dynamic range and signal-to-noise ratio are conceptually compared.

A 2.2M CMOS image sensor for high-speed machine vision applications

This paper describes a 2.2 Megapixel CMOS image sensor made in 0.18 μm CMOS process for high-speed machine vision applications. The sensor runs at 340 fps with digital output using 16 LVDS channels at 480MHz. The pixel array counts 2048x1088 pixels with a 5.5um pitch. The unique pixel architecture supports a true correlated double sampling, thus yields a noise level as low as 13 e- and a pixel parasitic light sensitivity (PLS) of 1/60 000. The sensitivity of the sensor is measured to be 4.64 Vlux.s and the pixel full well charge is 18k e-.

Characterization of Backside-Illuminated CMOS APS Prototypes for the Extreme Ultraviolet Imager On-Board Solar Orbiter

For the Extreme Ultraviolet Imager (EUI) of the Solar Orbiter mission, to be launched in 2017, CMOS active pixel sensor (APS) prototypes have been developed with several test pixel designs. A set of measurements was carried out to evaluate their performance characteristics in visible and in extreme ultraviolet wavelengths. We present the results of measurement campaigns that lead to the selection of a preferred pixel design in regard to the scientific performance requirements of the EUI flight model detectors, i.e., back-thinned CMOS APS devices of 2048 × 2048 and 3072 × 3072 pixel formats with a 10-μm pixel pitch.

Design and characterization of radiation tolerant CMOS image sensor for space applications

In this paper, we address the issues of designing a CMOS image sensor for space applications. The performance of a 4T pinned photodiode pixel under irradiation is shown and an example of a CMOS image sensor designed for sun tracking is given. It has been shown that the radiation tolerance level of the pixel is improved by using more advanced pixel architecture and more advanced fabrication process. Special measures are required in the sensor design to increases the sensor immunity on single event upset and latch-up.

6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications

In todays airborne mapping applications, there is a strong push towards higher-resolution sensors for high-end digital systems. This large-format sensor development aims to reduce the data acquisition (flight) time and cost, leading to higher productivity for the end-user. Due to the increased sensor resolution, these new systems allow higher flight altitude for the same ground sampling distance (GSD), thereby covering substantially larger swath width (distance covered across track during flight). Alternatively, at similar altitude, the system will deliver higher ground resolution. The described sensor exceeds the highest pixel count of sensors used for aerial mapping applications reported in a recent survey paper [1].