Jan Broulim

LDPC error correction code utilization

The paper presents a flexible construction of LDPC error correcting codes and an implementation of a code in a small microcontroller. A chosen short wordlength code was tested on the microcontroller platform and there were performed measurements focused on the error rate.

LDPC code optimization based on Tanner graph mutations

The paper presents LDPC error correcting code optimization based on Tanner graph mutations. A statistical experiment focused on a heuristic LDPC code construction was performed with the genetic algorithm. The algorithm used is briefly described. Short wordlength LDPC code optimization was simulated. Results of these simulations are summarized in this paper.

Boost power factor correction topology with average current control

This paper presents experimental results of a power factor corrector (PFC) with the average current control. Nowadays, we need a power factor corrector for most switch mode power supplies. Usually, a boost corrector with the average current control is used. The average current control offers good noise immunity, small input ripple and stability. Main paper goal was explaining average current shaping technique. We designed PFC with average current control and tested it in range 50 - 500 W. The experimental results proved benefits and drawbacks of this control technique.

Principle of Power Factor Corrector with Critical Conduction Mode

In recent years, interest in the application of the Power Factor Corrector has grown considerably. This paper gives a comprehensive account of Critical Conduction Mode (CrM) in the Power Factor Corrector. The Critical Conduction Mode technique is newer than Continuous Conduction Mode (CCM). The analysis shows the principle which are based on structural schema and mathematical description of the waveforms. We showed by the mathematical description that the frequency of the waveform depends on two factors. The first factor depends on input voltage and power. The second one determines the frequency of the mains half period.

Genetic optimization of a short block length LDPC code accelerated by distributed algorithms

In this paper we propose an application of genetic optimization algorithms to the construction of LDPC codes with interesting correcting capabilities. A short block length (64,56) code is constructed by the accelerated genetic optimization. A highly significant acceleration of the convergence speed is achieved by the coarse grained parallelization algorithm. The best optimized (64,56) LDPC code and its comprehensive evaluation are given in the paper.

LDPC (512,480) genetic design as alternative to CRC in implementation of AODV routing protocol stack

This paper presents a design of LDPC (Low Density Parity Check) code. Algorithm deals with code optimization based on Tanner graph mutations. The LDPC code was designed to replace CRC (Cyclic Redundancy Check) code in the application of a tiny AODV routing protocol stack. Own AODV routing protocol stack was previously designed especially for wireless sensor networks with constrained resources and it is intended for usage in wireless mesh network formed by Intelligent firemen suits. Link layer of target platform uses 64B long packet with 4B for LDPC parity. The code was designed to provide the most optimal detection and correction capability with the lowest possible parity bites.

Compact device for detecting single event effects in semiconductor components

The paper describes a compact system for detecting Single Event Effects (SEE) in semiconductor components. The SEE is caused by a hit into a electronic chip with an energetic particle. The hit can cause unexpected behaviour of the system. The tested component is called Device Under Test (DUT). The structure of the system is shown and used components are described with their main tasks. Some of results of the running system are shown.

Fully parallel FPGA decoder for irregular LDPC codes

One of the most significant current discussions in error correction coding is on the replacement of state-of-the-art codes by new innovative solutions. We propose a scalable parallel FPGA architecture for LDPC decoding. Regular and irregular codes are supported by the presented architecture. The architecture can be easily utilized in hardware applications. The performance of synthetized decoders is presented.

Very high resolution time measurement in FPGA

The paper describes possibility of time measurement in FPGA with very high resolution. There are described methods to obtain the resolution. Block diagram of the design which is implemented in FPGA are shown. Simulations and measurements are mentioned to prove the resolution.

The interface for the pixelated particle detector with the capability of the spectroscopy function and the coincidence measurement operation

An article describes design of the advanced interface primarily dedicated for the silicon pixelated particle detector of the Medipix family. The interface allows to gain information from the pixelated matrix and also to gain spectroscopy information from the common electrode of the pixelated detector. There is also described an implemented functionality enabling applications of the device in the coincidence measurement.