Jan Burchard

Towards mixed structural-functional models for algebraic fault attacks on ciphers

Fault attacks are a major threat for hardware-implemented security primitives, and algebraic techniques (equation-solving) are one of the most powerful building blocks for such attacks. We show that structural models obtained from a circuit implementation of the analyzed cipher can lead to more efficient attacks than the functional models used in literature. We also discuss possible synergies of the traditional functional and the proposed structural models and show first results on mixed models that combine structural and functional information. The overspecification provided by the mixed models creates an optimization potential through a partial mixed model with different filter rules for the combination of the two models.

Laissez-Faire Caching for Parallel #SAT Solving

The problem of counting the number of satisfying assignments of a propositional formula (#SAT) can be considered to be the big brother of the well known SAT problem. However, the higher computational complexity and a lack of fast solvers currently limit its usability for real world problems.

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG

Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in todays VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation methods, including new cell aware tests that explicitly target open defects, ignore the possibility of hazard caused test invalidation. Such tests can fail to detect a significant fraction of the targeted opens. In this work we present a waveform-accurate hazard-aware test generation approach to target intra-gate opens. Our methodology is based on a SAT-based encoding and allows the generation of tests guaranteed to be robust against hazards. Experimental results for large benchmarks mapped to the state-of-the-art NanGate 45nm cell library including complex cells show the test generation efficiency of the proposed method. Large circuits were efficiently handled — even without the use of fault simulation. Our experiments show that on average, about 10.92 % of conventional hazard-unaware tests will fail to detect the targeted opens because of test invalidation — these are reliably detected by our new test generation methodology. Importantly, our approach can also be applied to improve the effectiveness of commercial cell aware tests.

Integrating Algebraic and SAT Solvers

For solving systems of Boolean polynomials whose zeros are known to be contained in \(\mathbb {F}_2^n\), algebraic solvers such as the Boolean Border Basis Algorithm (BBBA) and SAT solvers use very different and possibly complementary methods to create new information. Based on suitable implementations of these solvers and conversion methods from Boolean polynomials to SAT clauses and back, we describe an automatic framework integrating the two solving techniques and exchanging newly found information between them. Using examples derived from cryptographic attacks, we present some initial experiments indicating the efficiency of this combination.

Evaluating the effectiveness of D-chains in SAT-based ATPG

With the ever increasing size of todays Very-Large-Scale-Integration (VLSI) designs new approaches for test pattern generation become more and more popular. One of the best known methods is SAT-based automatic test pattern generation (ATPG) which, in contrast to classical structural ATPG, first generates a mathematical representation of the problem in form of a Boolean formula. A specialized solver evaluates this representation to determine the testability of faults and extracts a test pattern in case a satisfying assignment was found. In order to increase the solving speed [1] introduced the concept of D-chains which add additional information to the mathematical model. In return, this forces the solver to only consider assignments that might lead to a valid test pattern and thus reduce the search space. With the advent of incremental solving new concepts like the backward D-chain or even more recently an indirect D-chain were introduced. However, none of the previous publications tried to analyze and evaluate which of these methods is the most beneficial. In this paper we present a thorough investigation of the different D-chain concepts to evaluate which is the best method for different problems. In addition, we propose a new indirect D-chain algorithm with two extensions. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

Efficient SAT-based generation of hazard-activated TSOF tests

With an increasing number of complex cells in todays VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. This is because CMOS circuits experience a large number of hazards during circuit inputs switching which are not modeled by classical tools. Hazards may activate some TSO faults considered untestable by classical ATPGs. The generation of tests that target such hazard activated opens can result in a very significant DPPM improvement - if used. In this paper, we present the first deterministic methodology for targeting hazard activated opens. It is based on a waveform-accurate SAT-based modeling and allows to accurately determine if a TSOF is detectable by hazard activation - or not. In addition, we provide a thorough investigation of the additionally achievable fault coverage using the state-of-the-art NanGate 45nm as well as NanGate 15nm cell libraries.

Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG

The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

Distributed Parallel #SAT Solving

The #SAT problem, that is counting the number of solutions of a propositional formula, extends the well-known SAT problem into the realm of probabilistic reasoning. However, the higher computational complexity and lack of fast solvers still limits its applicability for real world problems. In this work we present our distributed parallel #SAT solver dCountAntom which utilizes both local, shared-memory parallelism as well as distributed (cluster computing) parallelism. Although highly parallel solvers are known in SAT solving, such techniques have never been applied to the #SAT problem. Furthermore we introduce a solve progress indicator which helps the user to assess whether the presented problem is likely solvable within a reasonable time. Our analysis shows a high accuracy of the estimated progress. Our experiments with up to 256 CPU cores working in parallel yield large speedups across different benchmarks derived from real world problems: With the maximum number of available cores dCountAntom solved problems on average 141 times faster than a single core implementation.

Advanced Projects and Applications for Embedded Systems Engineering on E2LP Platform

The E2LP-Platform is capable to impart many different fields of learning content. Starting from simple, short exercises also complex projects can be realized covering up to several weeks of workload. This work presents a documentation of four students projects developed and performed at University of Freiburg in the Advanced Embedded System Laboratory. This laboratory contains a dynamic classroom approach in which the required laboratory hardware is mobile. Exploring real-wold challenges and problems motivates the participants to acquire a deeper knowledge.