Jan-Erik Mueller

Optimization of EDGE terminal power amplifiers using memoryless digital predistortion

This paper describes a lookup-table (LUT)-based digital predistortion system usable for enhanced data for global system for mobile evolution (EDGE) handset transmitters. The system is memoryless and capable of improving average efficiency and performance in terms of the leakage power at offset frequencies and error vector magnitude. The obtainable efficiency at maximum linear output power is comparable, but at backoffs superior to commercial EDGE power amplifiers (PAs). Minimum system requirements on word length and LUT size have been investigated, which shows that a LUT having approximately 500 coefficients and a system word length of 13 bits are sufficient for EDGE. The proposed system is simple compared to basestation implementations comprising PA memory compensation and can be easily implemented in handsets in order to improve the overall system performance. The effects of antenna mismatch on system performance have been investigated

Requirements for reconfigurable 4G front-ends

This talk will present the stringent requirements of 4G systems, and the goals that reconfigurable circuits must achieve for a successful insertion in multi-band 4G front-ends. Despite of ever increasing number of bands, modes and radios, mobile phones need to be kept at reasonable form factor, cost, performance and power consumption. The RF front-end develops more and more to a bottleneck limiting cost, size and performance of future radios. This introduces challenging, but also very attractive insertion opportunities for tunable and reconfigurable devices based on GaAs/SOI/SOS/BST or MEMS technologies.

A 1.8GHz wide-band stacked-cascode CMOS power amplifier for WCDMA applications in 65nm standard CMOS

A two-stage power amplifier (PA) for WCDMA operation in standard 65-nm CMOS is presented. The power amplifier delivers a saturated output power of 29.4 dBm at a power-added efficiency of 51% operating from a 3.4V supply at 1.8GHz. A two-stage interstage matching network was employed to achieve a high bandwidth of more than 300MHz where the amplifier shows a high PAE of more than 45%. With a WCDMA input signal a maximum linear output power (@ ACLR=−33 dBc) of 25.4 dBm was measured, corresponding to a linear PAE of 37.9% without digital predistortion (DPD). Using DPD, these figures could be improved to 27.9 dBm and 48%.

A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages

A novel, high ruggedness power amplifier topology in a 65-nm CMOS technology is proposed. The proposed stacked cascode topology uses only standard devices available in a modern triple-well CMOS process to achieve breakdown voltages of more than 18V. The power amplifier stage delivers 28 dBm output power at a power-added efficiency (PAE) of 69.9% from a 3.6V supply. The saturation gain is 18 dB. A watt-level power amplifier for GSM low-band operation with 31-dBm output power and 61% PAE is presented.

Mobile phone power amplifier linearity and efficiency enhancement using digital predistortion

The new generation mobile communication systems using spectrum efficient linear modulation schemes (QPSK, 8PSK, QAM) need linear power amplifiers in the transmission path to have good ACPR and EVM values. Linearization methods can be used to increase the linearity of the power amplifiers (PA). However, it is not reasonable to use complicated, power consuming and high cost systems. This paper presents a digital predistortion implementation for WCDMA signals using an FPGA (Field Programmable Gate Array) as DSP and investigates the application of this system in handsets. The method applied requires minimum change in the conventional transmitter path configuration but considerable PAE improvement can be achieved.

RF, Analog and Mixed Signal Technologies for Communication ICs - An ITRS Perspective

The International Technology Roadmap for Semiconductor (ITRS) Radio Frequency and Analog/Mixed-Signal (RF and AMS) Wireless Technology Working Group (TWG) addresses device technologies for wireless communications covering both silicon and III-V compound semiconductors. This paper discussed the roadmap and the figures of merit (FoM) used to characterize both active and passive devices critical for typical radio front end designs. The trends, challenges and potential solutions was reviewed and address the intersection of silicon and III-V compound semiconductors

Advanced transmitters with combined crest factor reduction and digital predistortion techniques

This paper analyses the benefits of combining crest factor reduction (CFR) technique and digital predistortion (DPD). DPD and CFR have been mainly investigated separately, and this is the contribution to the state of the art given here. The combination is attractive in modern wireless transmission systems due to the high peak-to-average-power-ratio (PAPR) of the signals employed. In these cases, the compression of the signal peaks performed by the amplifier in strong saturation region causes uncontrolled in-band and out-of-band distortion that degrades ACLR and EVM of the output signal. The joint architecture can take advantage from the improved linear output power given by DPD together with a controlled reduction of the peaks performed by CFR. The PA can in this way deliver a higher linear output power having at the same time a predictable linearity of the output RF signal. The concept has been implemented and tested on a commercial GaAs PA, obtaining an increased linear output power of 1.9 dB compared to the standalone PA when a WCDMA signal with PAPR of 3.47 dB is employed.

Identification of frequency dependent memory effects and the linearization of a CMOS PA for multiple standards

This paper presents a method to quantitatively identify memory effects. The accurate determination of characteristic curves for the rising and falling part of demodulated two tone signals provides precise hysteresis loops as a measure of memory effects.The method is applied to a CMOS power amplifier with a maximum peak power of 28 dBm fabricated in a 130nm technology. In the range from 1 kHz to 10MHz several memory effects at different frequencies are extracted. However, dominant effects are visible below 30kHz. The successful linearization of the power amplifier for multiple standards including narrow-band (EDGE) and wideband modulated signals (UMTS,WLAN)is demonstrated.All EVM and ACPR constraints are fulfilled with margin up to the maximum theoretically achievable linear power. The measurement results indicate that wideband modulated signals are less effected by memory effects compared to narrowband modulated signals.

A Memoryless Semi-Physical Power Amplifier Behavioral Model Based on the Correlation Between AM–AM and AM–PM Distortions

A new semi-physical memoryless computationally effective behavioral model (BM) capable of predicting amplitude-modulation-to-amplitude-modulation (AM-AM) and amplitude-modulation-to-phase-modulation (AM-PM) distortions is proposed. In recent years, AM-AM and AM-PM distortions have been separately studied in literature. Here, we investigate the correlation between AM-AM and AM-PM distortions first. Based on the observed correlation, a novel AM-PM model is derived from the well-known Rapp AM-AM model. On the basis of the close relationship between the AM-AM and AM-PM model, a highly accurate and computationally effective large-signal BM is obtained. The newly developed model addresses the current needs of the mobile industry that requires BMs of the power amplifier (PA), which can be interpreted by the designers. In addition, the models must be computationally effective due to the limited computation power in mobile handset. Therefore, only memoryless BMs can be taken into account and larger errors are accepted for the sake of computational effectiveness. In this paper, it is shown that the newly introduced model achieves excellent results, when it is applied to actual industrial applications of two GaAs-based class-AB PAs in 65-nm technology and one CMOS-based class AB PA in 28-nm technology, which are designed for mobile communications.

An extension of power amplifier behavioral models for optimizing battery current at system level

One of the most significant figures of merit concerning a power amplifier is its efficiency. However, the behavioral models of power amplifiers are mainly focused on the functional aspects, but not on current consumption. Therefore, simulations with respect to the efficiency of a power amplifier cannot be accomplished at the system level. To close the gap of simulation capabilities, this article proposes a time efficient and accurate extension of behavioral models to predict current consumption. For a commercial handset power amplifier, an average error of 1.9% between the fast high-level model and the measurement results is obtained.