Jochen Rascher

A Memoryless Semi-Physical Power Amplifier Behavioral Model Based on the Correlation Between AM–AM and AM–PM Distortions

A new semi-physical memoryless computationally effective behavioral model (BM) capable of predicting amplitude-modulation-to-amplitude-modulation (AM-AM) and amplitude-modulation-to-phase-modulation (AM-PM) distortions is proposed. In recent years, AM-AM and AM-PM distortions have been separately studied in literature. Here, we investigate the correlation between AM-AM and AM-PM distortions first. Based on the observed correlation, a novel AM-PM model is derived from the well-known Rapp AM-AM model. On the basis of the close relationship between the AM-AM and AM-PM model, a highly accurate and computationally effective large-signal BM is obtained. The newly developed model addresses the current needs of the mobile industry that requires BMs of the power amplifier (PA), which can be interpreted by the designers. In addition, the models must be computationally effective due to the limited computation power in mobile handset. Therefore, only memoryless BMs can be taken into account and larger errors are accepted for the sake of computational effectiveness. In this paper, it is shown that the newly introduced model achieves excellent results, when it is applied to actual industrial applications of two GaAs-based class-AB PAs in 65-nm technology and one CMOS-based class AB PA in 28-nm technology, which are designed for mobile communications.

A classification and comparative overview of state-of-the-art analog linearization techniques for integrated CMOS power amplifiers

A classification and comparison of state-of-the-art analog PA linearization techniques was conducted to identify which are suitable for handsets with digitally modulated signals (eg.WCDMA). Device and circuit level linearization methods are insufficient as standalone techniques although they are the least complex. However, their incorporation within system level adaptive predistorters shall alleviate the complexity. Such a combination of hybrid (device-circuit-system) level linearization methods would provide the solution to trade-off complexity and amount of linearity improvement. A hybrid-level linearization technique is hereby proposed to benefit from the advantages of device and circuit level linearization with low extra power consumption while chip area is preserved for terminal applications.

A CMOS RF front-end IC for multi antenna diversity applications in the S-band

In recent years the reception of audio broadcast signals via satellite has become popular, especially in the United States with the SDARS-system, supplying high quality broadcast services in particular to customers with mobile usage scenarios like in cars. There, the problem of reception impairments due to multipath wave propagation in urban areas or influences from dense foliage of the surrounding vegetation affects the broadcast quality. A possibility to minimize signal interruptions and to enhance the reception quality is the application of fast switchable multi antenna diversity receivers. In this paper we present the concept of an integrated RF front-end IC for such a system and describe the design of several important building blocks. The circuits are implemented in a 150 nm CMOS technology from LFoundry in Landshut, Germany.

A 30GHz bandwidth driver amplifier with high output voltage swing for ultra-wideband localization- and sensor systems

This paper reports on the analysis, design and characterization of a 30 GHz lumped broadband driving amplifier for ultra-wideband localization and sensor systems. The circuit integrates a cascode differential stage, which is fed by two cascaded emitter-followers (EF). The differential gain is 10 dB with a gain flatness of plusmn1 dB in the desired frequency range. This amplifier exhibits an output 1-dB compression point of 12 dBm. The maximum differential output voltage swing is 3.2 Vpp. The amplifier consumes a power of 560 mW at a supply voltage of plusmn3.3 V. The compact 0.5 mm2 amplifier is manufactured in a low-cost 0.25 mum SiGe BiCMOS technology with a transit frequency of 75 GHz.

A semi-physical power amplifier behavioral model capable of predicting gain expansion effects

A novel semi-physical power amplifier (PA) behavioral model (BM) that describes the input-output characteristic of PAs exhibiting gain expansion (GE) is introduced. The accurate prediction of GE is of particular importance because GE typically improves the power added efficiency (PAE) at high input powers. Though, GE impacts the spectral regrowth. Therefore, BMs that are capable of predicting GE, like the one introduced in this work, are highly desirable. In a case study, the proposed model is employed to predict the AM-AM distortions of a GaAs class AB PA designed for LTE applications. Excellent agreement between measurement and simulation results is obtained. The computational efficient model allows system-level simulations of advanced transmitter systems in order to optimize their modes of operation.

A comparative overview of high power handling CMOS switches and their recent applications in RF front ends

In this publication, techniques for high power handling capability of RF switches in bulk CMOS are investigated and compared. These allow reconfigurable power amplifiers (PAs) or radio front ends for Watt level communication standards if combined with approaches for high isolation. Special care is taken to assess the applicability of the solutions for monolithic integration in scaled CMOS processes. Results are shown with power handling capability as high as 34dBm in a 32nm CMOS process. Recent applications for RF switches in front ends or reconfigurable PAs are analyzed. They enable large DC current reduction in back-off with stage bypassing and load adaptation concepts. Up to 50% DC current reduction for low output power is reported. This greatly improves the average PA efficiency for varying envelope signals without the efforts of more sophisticated solutions like envelope tracking.

Time-efficient adjacent channel power ratio simulation utilizing Overlap-add signal decomposition for UMTS power amplifiers

The suitability of an RF power amplifier (PA) for modern sophisticated modulation schemes demands high linearity. One of the most significant figures of merit concerning PA linearity is its adjacent channel power ratio (ACPR). The aim of this paper is to propose a time-efficient simulation procedure for ACPR which conforms with the latest 3GPP TS 25.101 specifications for its calculation. This procedure overcomes the time penalty associated with the traditional envelope-based simulation method. The approach is based on standard harmonic balance (HB) tools with MATLAB post-processing incorporating the Overlap-add (OLA) signal decomposition DSP technique for fast RRC filtering. In addition, the simulation results are compared with measurements of a commercial WCDMA PA for verification. Accuracies of better than 0.5dB and 1.1dB are achieved up to 10dB and 2dB backoff respectively.