Jan Peter Karel Van Koetsem

Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways

Architectural studies have identified field-programmable gate arrays (FPGA) as a class of general-purpose very large scale integration components that could benefit from the introduction at the logic level of state-of-the-art massively parallel optical inter-chip interconnections. In this paper, we present a small-scale optoelectronic multi-FPGA demonstrator in which three optoelectronic enhanced FPGAs are interconnected by 2D Plastic Optical Fiber (POF) ribbon arrays. The full-custom FPGA chips consisting of an 8 X 8 array of very simple programmable logic cells are equipped with two optical sources and two receivers per FPGA cell yielding a maximum of 256 optical links per chip. The optical links are designed for signaling rates of 80 to 100 Mbit/s (160 to 200 Mbaud using Manchester coded data) compatible with the maximum clock frequency of the, in 0.6 micrometers CMOS implemented, FPGA chips. The results of parallel link experiments between such modules with both VCSELs and LEDs as sources will be shown. A large scale parallel bit error rate experiment at 90 Mbit/s/channel between two half-populated VCSEL-based FPGA modules with 112 of their 128 channels operational at bit error rates below 10-13 on all active channels (approximately equals 10 Gbit/s/chip) proves the feasibility of this approach. We first briefly discuss the general architecture and the realization of the optoelectronic FPGA demonstrator system. We then present measurement results on the available modules, followed by some conclusions on this work.

A parallel optical interconnect link with on-chip optical access

This paper describes a complete technology family for parallel optical interconnect systems. Key features are the two-dimensional on-chip optical access and the development of a complete optical pathway. This covers both chip-to-chip links on a single boards, chip-to-chip links over an optical backpanel, and even system-to-system interconnects. Therefore it is a scalable technology. The design of all parts of the link, and the integration of parallel optical interconnect systems in the design flow of electronic systems is presented in this paper.

Optical area I/O enhanced FPGA with 256 optical channels per chip

It is our goal to demonstrate the viability of massively parallel optical interconnections between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Field-programmable gate arrays (FPGA) have been identified as a class of general-purpose very large scale integration components that could benefit from the massive introduction of state-of-the-art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 X 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three- chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discuss the general architecture of our demonstrator system and the realization of the optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.

Microcavity LED-based parallel data link using small-diameter (125-μm) plastic optical fibers

Parallel optical data links using high efficiency Microcavity LEDs and small diameter POF ribbons are proposed. MCLED performance, coupling efficiencies, alignment tolerances, POF end facet termination techniques and first link experiments are studied.