Jan W. Slotboom

Computer-aided two-dimensional analysis of bipolar transistors

A method for solving numerically the two-dimensional (2D) semiconductor steady-state transport equations is described. The principles of this method have been published earlier [1]. This paper discusses in detail the method and a number of considerable improvements. Poissons equation and the two continuity equations are discretized on two networks of different rectangular meshes. The 2D continuity equations are approximated by a set of difference equations assuming that the hole and electron current density components along the meshlines are constant between two neighboring meshpoints in a way similar to that used by Gummel and Scharfetter [2] for the one-dimensional (1D) continuity equations. The resulting difference approximations have generally a much larger validity range than the conventional difference formulations where it is assumed that the change in electrostatic potential between two neighboring points is small compared with k T/q . Therefore, a much smaller number of meshpoints is necessary than for the conventional difference approximations. This reduces considerably the computation time and the required memory space. It will be shown that the matrix of the coefficients of this set of difference equations is always positive definite. This is an important property and guarantees convergence and stability of the numerical solution of the continuity equations. The way in which the difference approximations for the continuity equations are derived gives directly consistent expressions for the current densities that can be used for calculating the currents. In order to demonstrate the kind of solutions obtainable, steady-state results for a bipolar n-p-n silicon transistor are presented and discussed.

Non-local impact ionization in silicon devices

In small bipolar and MOS transistors, the electrons gain much less energy than according to the maximum electric field. This is due to nonlocal electron heating and the small width of the E-field peak. The simplified energy balance equation with the energy relaxation length lambda /sub e/ as parameter gives the electron temperature for a given electric field distribution. From a series of MBE (molecular beam epitaxy)-grown bipolar transistors and scaled submicron MOS transistors, lambda /sub e/=650 AA was found. With the calculated temperature distribution and known empirical models for the impact ionization, avalanche (substrate) currents are accurately predicted. This procedure can easily be implemented, as postprocessing, in existing device simulators with hardly any extra computation time. It extends in a consistent way the validity range of these simulators to future device generations.<<ETX>>

Parasitic energy barriers in SiGe HBTs

Parasitic energy barriers can easily be introduced during processing. Measurements and calculations of experimental n-p-n HBTs (heterojunction bipolar transistors) are presented, showing that a parasitic conduction-band barrier at the base-collector junction reduces the collector current and the cutoff frequency. A simple analytical model explains the f/sub T/ degradation, caused by the reduction of the collector current and a pileup of minority carriers in the base. With the model the effective height and width of the barrier can also be derived from the measured collector current enhancement factor I/sub C/(SiGe)/I/sub C/(Si).<<ETX>>

THE EVOLUTION OF THE MINIMOS MOBILITY MODEL

Abstract The paper reviews the evolution of the mobility model of the MINIMOS program for the two-dimensional simulation of miniaturized MOS devices over a period of 10 years.

Surface impact ionization in silicon devices

In the past, carrier ionization rates in the silicon bulk have been measured and reported extensively. We present experiments and accurate electric field calculations for deriving the surface impact ionization rate of electrons. It is given by\alpha_{n}(surface) = 2.45 \cdot 10^{6} \cdot \exp(-1.92.10^{6}/E)[cm-1] Due to the lower mean free path at the surface, this ionization rate is much smaller then the well known bulk values and falls-off more steeply for low electric fields. The consequences for the simulation of MOS substrate currents will be shown.

Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy

High-quality SiGe heterojunction bipolar transistors (HBTs) have been fabricated using material grown by molecular beam epitaxy (MBE). The height of parasitic barriers in the conduction band varied over the wafer, and the influence of these barriers on controller current, early voltage, and cutoff frequency were studied by experiments and simulations. Temperature-dependent measurements were performed to study the influence of the barriers on the effective bandgap narrowing in the base and to obtain an expression for the collector-current enhancement. From temperature-dependent measurements, the authors demonstrate that the collector-current enhancement of the HBTs can be described by a single exponential function with a temperature-independent prefactor.<<ETX>>

Impact of silicon substrates on leakage currents

Leakage currents of n+-p-diodes, made on four different groups of p-type silicon substrates, are investigated at temperatures between 50 and 120°C. At these temperatures, diffusion of thermally generated minority carriers from the bulk is the dominant leakage current mechanism and determines the holding time of dynamic memories. Measurements at these temperatures show that for Czochral-sky-grown wafers (CZ) with a high interstitial oxygen concentration as is used for intrinsic gettering, the leakage current densities are about 1O× higher than for CZ wafers with a low oxygen concentration or floating-zone wafers (FZ), and are about 100× higher than for p-p+-epitaxial substrates. Simple analytical formulas explaining these large differences will be presented. Finally a short discussion about the optimum substrate for future high-density memories will be given.

Selective-epitaxial base technology with 14 ps ECL-gate delay, for low power wide-band communication systems

A silicon bipolar technology is presented that incorporates a selectively epitaxially grown base in a double-polysilicon transistor. Si-bases as well as Si-SiGe-multilayer bases are applied. Both result in excellent device performance, with cut-off and maximum oscillation frequencies up to 45 GHz, and ECL-gate delays down to 13.7 ps. DC-coupled broad-band amplifiers for 15 Gbit/s optical data links have been fabricated, providing record bandwidths of 13.2 GHz. As selective epitaxial growth is performed at 700/spl deg/C in a production epitaxial reactor, this technology can easily be combined with current semiconductor manufacturing technology.

Impact ionization in thin silicon diodes

We study the breakdown behavior of thin, abrupt silicon pin-diodes, using a low-power optical technique which can directly measure the avalanche multiplication factors even in the presence of large tunneling currents. Our measurements agree with a simple model for nonlocal avalanche generation, and we use this model to extend the breakdown predictions to a broad class of doped diodes similar to those found in the base-collector region of bipolar devices. Based on this analysis, we make quantitative estimates for the BV/sub CEO/ breakdown of modern Si and SiGe high-speed bipolar transistors.

A Digital Field Memory for Television Receivers

In this paper a description and a specification are presented of a 308 kbit digital field memory chip. This device, which is manufactured in a 2 um NMOS process and operates up to 40 MHz, has been designed especially for video applications. Aspects of the design are highlighted with respect to the application in television receivers.