Janardhan H. Satyanarayana

HEAT: hierarchical energy analysis tool

This paper presents an algorithm for the estimation of power in static CMOS digital circuits using a stochastic approach. The salient feature of this approach is that it can be used to estimate the power of reasonably large digital circuits in a very short time, due to its hierarchical nature. Here, the given circuit is first partitioned into smaller sub-circuits. Then, the sub-circuits are modeled using state transition diagrams (stds), and the steady-state probabilities associated with the various states are computed by treating them as irreducible Markov chains. Finally, the energy associated with each sub-circuit is computed, and the total energy of the circuit is obtained by summing up the energies of its constituent sub-circuits. In the proposed hierarchical approach, the energies associated with various edges in a subcircuit are calculated only once using SPICE and these values are used several times; this results in large savings in computation time. Another advantage of the proposed approach is that we can accommodate switching activities at the transistor level and not necessarily at gate or higher levels. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations, but the computation time required by the proposed approach is orders of magnitude less than that of SPICE.

Systematic design of high-speed and low-power digit-serial multipliers

Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of the digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes (/spl les/4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2W), where W represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption.

Design and implementation of low-power digit-serial multipliers

Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel design methodology is presented which permits bit-level pipelining of the digit-serial architectures. This achieves sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for transformed multipliers with smaller digit-sizes (/spl les/4), the singly-redundant multiplier consumes the least power and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2 W), where W represents the word-length. The proposed digit-serial multipliers consume on an average 20% lower power than the traditional digit-serial architectures for the non-pipelined case, and about 5-15 times lower power for the bit-level pipelined case. Also, modified Booth (1951) recoding is applied to transformed multipliers and it is found that the recoded multipliers consume about 22% lower power than the transformed multipliers without recoding.

A theoretical approach to estimation of bounds on power consumption in digital multipliers

This paper presents a systematic theoretical approach for the analysis of bounds on power consumption in digital multipliers. This is because in many applications the maximum value of power consumption and not just the average power may be of importance to the designer. The maximum values can be used to predict the maximum battery life in portable applications and also determine the nature of heat sinks in nonportable applications. The proposed approach involves the development of state transition diagrams (stds) for the subcircuits making up the digital multipliers. The std is comprised of states and edges, with the edges representing a transition (switching activity) from one state to another in the subcircuit. Then, maximum (minimum) energy values associated with the edges constituting the stds are used to derive the upper (lower) bound. The multipliers analyzed in this paper include the Baugh Wooley multiplier, the binary tree multiplier, and the Wallace tree multiplier. The analysis is performed for both nonpipelined and p-bit-level pipelined multipliers. It is theoretically shown that there is a significant reduction in upper bound as p is decreased, with the lower bound being unaffected by the level of bit-pipelining. Experimental results are presented to show that the average power consumption values indeed lie within the predicted theoretical bounds, and that the theoretical upper bounds are quite tight.

Estimation of average energy consumption of ripple-carry adder based on average length carry chains

We show theoretically that the average energy consumption of a ripple-carry adder is O(W), and the upper bound on the average energy consumption is O(Wlog/sub 2/W), where W is the word-length of the operands. Our theoretical analysis is based on a simple state transition diagram (STD) model of a full adder cell and the observations that the average length of a carry propagation chain is v=2, and the average length of the maximum carry chain is v/spl les/log/sub 2/W. To verify our theoretical conclusions, we use the HEAT CAD tool to estimate the average power consumed by the ripple-carry adder for word-lengths 4/spl les/W/spl les/64. The experimental results show that, for W/spl ges/16, the error in our theoretical estimations is around 15%.

Low-power digit-serial multipliers

Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (/spl les/4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.

Power estimation of digital data paths using HEAT

The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers

The paper presents a systematic theoretical approach for the analysis of bounds on power consumption in Baugh-Wooley, binary tree and Wallace tree multipliers. This is achieved by first developing state transition diagrams (STDs) for the sub circuits making up the multipliers. The STD is comprised of states and edges, with the edges representing a transition (switching activity) from one state to another in the sub circuit. Then, maximum (minimum) energy values associated with the edges constituting the STDs are used to derive the zipper (lower) bound in both non pipelined and p-bit level pipelined multipliers. It is shown that as p is decreased, the upper bound approaches the lower bound. Moreover, based on the theoretical analysis we conclude that the upper bound in a Baugh-Wooley multiplier has a cubic dependence on the word length, while that in a binary tree multiplier has a quadratic dependence on the word length.

A hierarchical approach to transistor-level power estimation of arithmetic units

This paper presents an algorithm for power estimation in digital circuits using a hierarchical approach. The salient feature of this approach is that it can be used to estimate the power of large digital circuits in a reasonably short time. Moreover, it takes into account both the spatial correlations introduced in the circuit due to reconvergent fanout, and the delays associated with the various computation units. The circuit is partitioned into sub-circuits which are modeled using state transition diagrams (STDs), and the energy, and therefore power, associated with the circuit is then computed from its constituent STDs by treating them as irreducible Markov chains. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations. However, the computation time required by the proposed approach is orders of magnitude less than that required by SPICE.